19-2538; Rev 2; 10/02
1:9 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
General Description
The MAX9326 low-skew, 1:9 differential driver features
extremely low output-to-output skew (50ps max) and
part-to-part skew (225ps max). These features make
the device ideal for clock and data distribution across a
backplane or board. The device repeats an HSTL or
LVECL/LVPECL differential input at nine differential out-
puts. Outputs are compatible with LVECL and LVPECL,
and directly drive 50Ω terminated transmission lines.
The differential inputs can be configured to accept a
single-ended signal when the unused complementary
input is connected to the on-chip reference output volt-
age V
BB.
All inputs have internal pulldown resistors to
V
EE.
The internal pulldowns and a fail-safe circuit
ensure differential low default outputs when the inputs
are left open or at V
EE
.
The MAX9326 operates over a +2.375V to +3.8V supply
range for interfacing to differential HSTL and LVPECL
signals. This allows high-performance clock or data dis-
tribution in systems with a nominal +2.5V or +3.3V sup-
ply. For LVECL operation, the device operates with a
-2.375V to -3.8V supply.
The MAX9326 is offered in 28-lead PLCC and space-
saving 28-lead QFN packages. The MAX9326 is speci-
fied for operation from -40°C to +85°C.
o
50ps (max) Output-to-Output Skew
o
1.5ps
RMS
(max) Random Jitter
o
Guaranteed 300mV Differential Output at 1.0GHz
o
+2.375V to +3.8V Supplies for Differential
HSTL/LVPECL
o
-2.375V to -3.8V Supplies for Differential LVECL
o
On-Chip Reference for Single-Ended Inputs
o
Outputs Low for Inputs Open or at V
EE
o
Pin Compatible with MC100LVE111
Features
MAX9326
Ordering Information
PART
MAX9326EQI
MAX9326EGI
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 PLCC
28 QFN 5mm x 5mm
Applications
Precision Clock Distribution
Low-Jitter Data Repeaters
Functional Diagram appears at end of data sheet.
Pin Configurations
V
CC
Q0
Q0
Q1
Q1
Q2
Q2
V
CC
TOP VIEW
Q0
Q0
Q1
Q1
Q2
28
27
26
25
24
23
V
EE
N.C.
CLK
V
CC
CLK
V
BB
N.C.
26
27
28
1
2
3
4
18
17
16
Q3
Q3
Q4
V
CC
Q4
Q5
Q5
V
EE
N.C.
CLK
V
CC
CLK
V
BB
N.C.
1
2
3
4
5
6
7
21
20
19
Q3
Q3
Q4
V
CC
Q4
Q5
Q5
MAX9326
15
14
13
12
MAX9326
22
18
17
16
15
Q6
25 24
23 22
21
20
19
5
6
7
Q7
8
9
10
Q6
11
Q6
Q8
Q8
V
CC
Q7
10
11
12
13
Q6
Q7
Q8
Q8
QFN*
*CORNER PINS AND EXPOSED PAD ARE CONNECTED TO V
EE
.
________________________________________________________________
Maxim Integrated Products
V
CC
Q7
PLCC
14
8
9
Q2
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1:9 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
MAX9326
ABSOLUTE MAXIMUM RATINGS
V
CC
- V
EE
...............................................................-0.3V to +4.1V
Inputs (CLK,
CLK)
to V
EE
...........................-0.3V to (V
CC
+ 0.3V)
CLK to
CLK
........................................................................±3.0V
Continuous Output Current .................................................50mA
Surge Output Current........................................................100mA
V
BB
Sink/Source Current................................................±0.65mA
Continuous Power Dissipation (T
A
= +70°C)
28-Lead PLCC (derate 10.5mW/°C above +70°C) .....842mW
θ
JA
in Still Air .............................................................+95°C/W
θ
JC
.............................................................................+25°C/W
28-Lead QFN (derate 20.8mW/°C above +70°C) .....1667mW
θ
JA
in Still Air .............................................................+48°C/W
θ
JC
...............................................................................+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model (CLK,
CLK,
Q_,
Q_)
.........................≥2kV
Soldering Temperature (10s) ...........................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
((V
CC
- V
EE
) = 2.375V to 3.8V, R
L
= 50Ω
±1%
to V
CC
- 2V. Typical values are at (V
CC
- V
EE
) = 3.3V, V
IH
= (V
CC
- 1V), V
IL
= (V
CC
-
1.5V).) (Notes 1–4)
PARAMETER
SYMBOL
CONDITIONS
-40°C
MIN
TYP
MAX
MIN
+25°C
TYP
MAX
MIN
+85°C
TYP
MAX
UNITS
DIFFERENTIAL INPUT (CLK_,
CLK_)
Single-Ended
Input High
Voltage
Single-Ended
Input Low
Voltage
Differential Input
High Voltage
Differential Input
Low Voltage
V
IH
Figure 1
V
CC
- 1.165
V
CC
V
CC
- 1.165
V
CC
V
CC
- 1.165
V
CC
V
V
IL
Figure 1
V
EE
V
EE
+ 1.2
V
EE
0.095
0.095
-10.0
V
CC
- 1.475
V
CC
V
CC
- 0.095
V
CC
- V
EE
3.0
+150.0
V
EE
V
EE
+ 1.2
V
EE
0.095
0.095
-10.0
V
CC
- 1.475
V
CC
V
CC
- 0.095
V
CC
- V
EE
3.0
+150.0
V
EE
V
EE
+ 1.2
V
EE
0.095
0.095
-10.0
V
CC
- 1.475
V
CC
V
CC
- 0.095
V
CC
- V
EE
V
V
IHD
V
ILD
Figure 1
Figure 1
(V
CC
- V
EE
)
<
3.0V, Figure 1
(V
CC
- V
EE
)
≥
3.0V, Figure 1
V
IH,
V
IL,
V
IHD,
V
ILD
V
V
Differential Input
Voltage
V
IHD -
V
ILD
V
3.0
+150.0
µA
Input Current
I
IN
2
_______________________________________________________________________________________
1:9 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
DC ELECTRICAL CHARACTERISTICS (continued)
((V
CC
- V
EE
) = 2.375V to 3.8V, R
L
= 50Ω
±1%
to V
CC
- 2V. Typical values are at (V
CC
- V
EE
) = 3.3V, V
IH
= (V
CC
- 1V), V
IL
= (V
CC
-
1.5V).) (Notes 1–4)
PARAMETER
SYMBOL
CONDITIONS
-40°C
MIN
TYP
MAX
MIN
+25°C
TYP
MAX
MIN
+85°C
TYP
MAX
UNITS
MAX9326
OUTPUT (Q_,
Q _
)
Single-Ended
Output High
Voltage
Single-Ended
Output Low
Voltage
Differential
Output Voltage
V
OH
Figure 2
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
- 1.085 - 0.977 - 0.880 - 1.025 - 0.949 - 0.88 - 1.025 - 0.929 - 0.88
V
V
OL
Figure 2
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
- 1.810 - 1.695 - 1.620 - 1.810 - 1.697 - 1.62 - 1.810 - 1.698 - 1.62
535
718
595
749
595
769
V
V
OH
- V
OL
Figure 2
mV
REFERENCE VOLTAGE OUTPUT (V
BB
)
Reference
Voltage Output
SUPPLY
Supply Current
I
EE
(Note 6)
35
50
39
55
42
65
mA
V
BB
I
BB
=
±0.5mA
(Note 5)
V
CC
V
CC
- 1.38 - 1.318
V
CC
-
1.26
V
CC
V
CC
V
CC
- 1.38 - 1.325 - 1.26
V
CC
V
CC
V
CC
- 1.38 - 1.328 - 1.26
V
_______________________________________________________________________________________
3
1:9 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
MAX9326
AC ELECTRICAL CHARACTERISTICS–PLCC Package
((V
CC
- V
EE
) = 2.375V to 3.8V, R
L
= 50Ω
±1%
to V
CC
- 2V, f
IN
≤
500MHz, input transition time = 125ps (20% to 80%). Typical values
are at (V
CC
- V
EE
) = 3.3V, V
IH
= V(V
CC
- 1V), V
IL
= (V
CC
- 1.5V).) (Note 7)
PARAMETER
Differential
Input-to-Output
Delay
Single-Ended
Input-to-Output
Delay
Output-to-
Output Skew
Part-to-Part
Skew
Added Random
Jitter
Added
Deterministic
Jitter
Switching
Frequency
Output Rise/Fall
Time (20% to
80%)
SYMBOL
t
PLHD
t
PHLD
t
PLH
t
PHL
t
SKOO
t
SKPP
CONDITIONS
-40°C
MIN
365
TYP
MAX
615
MIN
375
+25°C
TYP
MAX
605
MIN
383
+85°C
TYP
MAX
653
UNITS
Figure 2
ps
Figure 3 (Note 8)
350
635
360
685
360
705
ps
(Note 9)
Differential input
(Note 10)
f
IN
= 0.5GHz
clock pattern
(Note 11)
f
IN
= 1.0Gbps,
2E
23
- 1 PRBS
pattern (Note 11)
V
OH
- V
OL
≥
300mV clock
pattern
50
190
50
125
50
240
ps
ps
t
RJ
1.5
1.5
1.5
ps
RMS
t
DJ
95
95
95
ps
P-P
f
MAX
1.5
1.5
1.5
GHz
t
R
, t
F
Figure 2
140
440
140
440
140
440
ps
4
_______________________________________________________________________________________
1:9 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
AC ELECTRICAL CHARACTERISTICS–QFN Package
((V
CC
- V
EE
) = 2.375V to 3.8V, R
L
= 50Ω
±1%
to V
CC
- 2V, f
IN
≤
500MHz, input transition time = 125ps (20% to 80%). Typical values
are at (V
CC
- V
EE
) = 3.3V, V
IH
= V(V
CC
- 1V), V
IL
= (V
CC
- 1.5V).) (Note 7)
PARAMETER
Differential
Input-to-Output
Delay
Single-Ended
Input-to-Output
Delay
Output-to-
Output Skew
Part-to-Part
Skew
Added Random
Jitter
Added
Deterministic
Jitter
Switching
Frequency
Output Rise/Fall
Time (20% to
80%)
SYMBOL
t
PLHD
t
PHLD
t
PLH
t
PHL
t
SKOO
t
SKPP
CONDITIONS
-40°C
MIN
217
TYP
MAX
541
MIN
238
+25°C
TYP
MAX
448
MIN
249
+85°C
TYP
MAX
486
UNITS
MAX9326
Figure 2
ps
Figure 3 (Note 8)
213
558
230
506
244
503
ps
(Note 9)
Differential input
(Note 10)
f
IN
= 0.5GHz
clock pattern
(Note 11)
f
IN
= 1.0Gbps,
2E
23
- 1 PRBS
pattern (Note 11)
V
OH
- V
OL
≥
300mV clock
pattern
50
192
50
215
50
218
ps
ps
t
RJ
1.5
1.5
1.5
ps
RMS
t
DJ
95
95
95
ps
P-P
f
MAX
1.5
1.5
1.5
GHz
t
R
, t
F
Figure 2
97
411
104
210
111
232
ps
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Measurements are made with the device in thermal equilibrium.
Current into a pin is defined as positive. Current out of a pin is defined as negative.
DC parameters production tested at T
A
= +25°C and guaranteed by design over the full operating temperature range.
Single-ended input operation using V
BB
is limited to (V
CC
- V
EE
) = 3.0V to 3.8V.
Use V
BB
only for inputs that are on the same device as the V
BB
reference.
All pins open except V
CC
and V
EE
.
Guaranteed by design and characterization. Limits are set at
±6
sigma.
Measured from the 50% point of the input signal with the 50% point equal to V
BB
, to the 50% point of the output signal.
Measured between outputs of the same part at the signal crossing points for a same-edge transition. Differential input signal.
Measured between outputs of different parts under identical conditions for same-edge transition.
Device jitter added to the input signal. Differential input signal.
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5
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