19-0736; Rev 0; 1/07
2:1 Multiplexer and 1:2 Demultiplexer
with Loopback
General Description
The MAX9396 consists of a 2:1 multiplexer and a 1:2
demultiplexer with loopback. The multiplexer section
(channel B) accepts two differential inputs and gener-
ates a single differential output. The demultiplexer sec-
tion (channel A) accepts a single differential input and
generates two parallel differential outputs. The
MAX9396 features a loopback mode that connects the
input of channel A to the output of channel B and con-
nects the selected input of channel B to the outputs of
channel A.
The differential inputs of the MAX9396 accept
CML/LVPECL levels and can also accept LVDS inputs
with common-mode voltages from +0.6V to (V
CC
-
0.05V). The differential outputs are LVDS compatible
and drive 100Ω loads.
Three LVCMOS/LVTTL logic inputs control the internal
connections between inputs and outputs, one for the
multiplexer portion of channel B (BSEL), and the other
two for loopback control of channels A and B (LB_SELA
and LB_SELB). Independent enable inputs for each dif-
ferential output pair provide additional flexibility.
Fail-safe circuitry forces the outputs to a differential low
condition for undriven inputs or when the common-
mode voltage is below +0.6V.
Ultra-low 57ps
P-P
(typ) pseudorandom bit sequence
(PRBS) jitter ensures reliable communications in high-
speed links that are highly sensitive to timing error,
especially those incorporating clock-and-data recovery,
or serializers and deserializers. The high-speed switch-
ing performance guarantees 1.25Gbps operation and
less than 87ps (max) skew between channels.
The MAX9396 is available in a 32-pin TQFP package
and is specified over the -40°C to +85°C extended tem-
perature range.
Features
♦
Guaranteed 1.25Gbps Operation with 450mV (min)
Differential Output Swing
♦
Integrated 100Ω Resistors on Differential Inputs
♦
Simultaneous Loopback Control
♦
2ps
(RMS)
(max) Random Jitter
♦
AC Specifications Guaranteed for 150mV
Differential Input
♦
Signal Inputs Accept Any Differential Signals with
V
CM
= +0.6V to (V
CC
- 0.05V)
♦
LVDS Outputs for Clock or High-Speed Data
♦
Low-Level Input Fail-Safe Detection
♦
+3.0V to +3.6V Supply Voltage Range
♦
LVCMOS/LVTTL Logic Inputs
MAX9396
Ordering Information
PART
TEMP RANGE
PIN-
PACKAGE
32 TQFP
PKG
CODE
H32-1
MAX9396EHJ+ -40°C to +85°C
+Denotes
a lead-free package.
Typical Operating Circuit
+3.0V TO
+3.6V
0.1µF
0.01µF
V
CC
Z
0
= 50Ω
INA
OUTA0
Z
0
= 50Ω
100Ω
Z
0
= 50Ω
INA
OUTA0
Z
0
= 50Ω
Applications
High-Speed Telecom/Datacom Equipment
Central Office Backplane Clock Distribution
DSLAMs
Protection Switching
Fault-Tolerant Systems
LVCMOS/LVTTL
LOGIC INPUTS
MAX9396
INB0
INB0
INB1
INB1
ENA0
ENA1
ENB
OUTB
Z
0
= 50Ω
OUTB
Z
0
= 50Ω
OUTA1
Z
0
= 50Ω
OUTA1
Z
0
= 50Ω
LVDS
RECEIVER
LB_SELA
LB_SELB
BSEL
GND
GND
GND
GND
Pin Configuration and Functional Diagram appear at end of
data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
2:1 Multiplexer and 1:2 Demultiplexer
with Loopback
MAX9396
ABSOLUTE MAXIMUM RATINGS
V
CC
to GND ...........................................................-0.3V to +4.1V
IN_ _,
IN_
_, OUT_ _,
OUT_
_, EN_ _, BSEL, LB_SEL_
to GND....................................................-0.3V to (V
CC
+ 0.3V)
IN_ _ to
IN_
_..........................................................................±3V
Short-Circuit Duration (OUT_ _,
OUT_
_) ...................Continuous
Continuous Power Dissipation (T
A
= +70°C)
32-Pin TQFP (derate 13.1mW/°C above +70°C)........1047mW
Junction-to-Ambient Thermal Resistance in Still Air
32-Pin TQFP............................................................+76.4°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection (Human Body Model)
(IN_ _,
IN_
_, OUT_ _,
OUT_
_, EN_ _, BSEL, LB_SEL_)..±2kV
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, R
L
= 100Ω ±1%, EN_ _ = V
CC
, V
CM
= +0.6V to (V
CC
- 0.05V), T
A
= -40°C to +85°C, unless otherwise noted.
Typical values are at V
CC
= +3.3V, |V
ID
| = 0.2V, V
CM
= +1.2V, T
A
= +25°C.) (Notes 1, 2, and 3)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
DIFFERENTIAL INPUTS (IN_ _,
IN_
_)
Differential Input Voltage
Input Common-Mode Range
Single-Ended Input Current
Differential Input Termination
LVDS OUTPUTS (OUT_ _,
OUT_
_)
Differential Output Voltage
Change in Magnitude of V
OD
Between Complementary Output
States
Offset Common-Mode Voltage
Change in Magnitude of V
OS
Between Complementary Output
States
V
OD
∆V
OD
V
OS
∆V
OS
R
L
= 100Ω, Figure 2
Figure 2
Figure 2
Figure 2
1.4
1.5
450
540
600
50
1.6
50
mV
mV
V
mV
V
ID
V
CM
I
IN_ _
,
I
IN_
_
R
IN
|V
ID
|
≤
3.0V
(V
IN
= 0V to +V
CC
, IN_ _, or
IN_
_ open)
IN_ _ to
IN_
_
V
ILD
> 0V and V
IHD
< V
CC
, Figure 1
0.1
0.6
-15
80
100
3.0
V
CC
-
0.05
+200
120
V
V
µA
Ω
SYMBOL
V
IH
V
IL
I
IH
I
IL
V
IN
= +2.0V to V
CC
V
IN
= 0V to +0.8V
CONDITIONS
MIN
2.0
0
0
-1
TYP
MAX
V
CC
0.8
20
+10
UNITS
V
V
µA
µA
LVCMOS/LVTTL INPUTS (EN_ _, BSEL, LB_SEL_)
2
_______________________________________________________________________________________
2:1 Multiplexer and 1:2 Demultiplexer
with Loopback
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, R
L
= 100Ω ±1%, EN_ _ = V
CC
, V
CM
= +0.6V to (V
CC
- 0.05V), T
A
= -40°C to +85°C, unless otherwise noted.
Typical values are at V
CC
= +3.3V, |V
ID
| = 0.2V, V
CM
= +1.2V, T
A
= +25°C.) (Notes 1, 2, and 3)
PARAMETER
Output Short-Circuit Current
(Output(s) Shorted to GND)
Output Short-Circuit Current
(Outputs Shorted Together)
SUPPLY CURRENT
R
L
= 100Ω, EN_ _ = V
CC
Supply Current
I
CC
R
L
= 100Ω, EN_ _ = V
CC
, switching at
625MHz (1.25Gbps)
56
56
75
75
mA
SYMBOL
V
ID
=
±100mV
(Note 4)
CONDITIONS
V
OUT_ _
or V
OUT_
_
= 0V
V
OUT_ _
=
V
OUT_
_
= 0V
MIN
TYP
28
17
MAX
40
mA
24
12
mA
UNITS
MAX9396
|I
OS
|
|I
OSB
|
V
ID
=
±100mV,
V
OUT_ _
= V
OUT_
_
(Note 4)
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, f
IN
≤
625MHz, t
R_IN
= t
F_IN
= 125ps, R
L
= 100Ω ±1%, |V
ID
|
≥
150mV, V
CM
= +0.6V to (V
CC
- 0.075V), EN_ _ =
V
CC
, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V, |V
ID
| = 0.2V, V
CM
= +1.2V, f
IN
= 625MHz, T
A
=
+25°C.) (Note 5)
PARAMETER
SEL to Switched Output
Disable Time to Differential
Output Low
Enable Time to Differential Output
High
Data Rate
Low-to-High Propagation Delay
High-to-Low Propagation Delay
Pulse Skew |t
PLH
– t
PHL
|
Output Channel-to-Channel Skew
Output Low-to-High Transition
Time (20% to 80%)
Output High-to-Low Transition
Time (80% to 20%)
Added Random Jitter
Added Deterministic Jitter
SYMBOL
t
SWITCH
t
PHD
t
PDH
f
DR
t
PLH
t
PHL
t
SKEW
t
CCS
t
R
t
F
t
RJ
t
DJ
Figure 3
Figure 4
Figure 4
V
OD
> 450mV, 2
23
- 1 PRBS
Figures 1, 5
Figures 1, 5
Figures 1, 5 (Note 6)
Figure 6 (Note 7)
f
IN_ _
= 100MHz, Figures 1, 5
f
IN_ _
= 100MHz, Figures 1, 5
f
IN_ _
= 625MHz, clock pattern (Note 8)
1.25Gbps, 2
23
- 1 PRBS (Note 8)
170
170
220
210
0.45
57
1.25
250
250
340
355
18
630
630
86
87
350
350
2
120
CONDITIONS
MIN
TYP
MAX
1.1
1.7
1.7
UNITS
ns
ns
ns
Gbps
ps
ps
ps
ps
ps
ps
ps
(RMS)
ps
P-P
Measurements obtained with the device in thermal equilibrium. All voltages referenced to GND except V
ID
, V
OD
, and
∆V
OD
.
Current into the device defined as positive. Current out of the device defined as negative.
DC parameters are production tested at T
A
= +25°C and guaranteed by design and characterization for T
A
= -40°C to +85°C.
Current through either output.
Guaranteed by design and characterization. Limits set at ±6 sigma.
t
SKEW
is the magnitude difference of differential propagation delays for the same output over the same condtions. t
SKEW
=
|t
PHL
- t
PLH
|.
Note 7:
Measured between outputs of the same device at the signal crossing points for a same-edge transition under the same con-
ditions. Does not apply to loopback mode.
Note 8:
Device jitter added to the differential input signal.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
_______________________________________________________________________________________
3
2:1 Multiplexer and 1:2 Demultiplexer
with Loopback
MAX9396
Typical Operating Characteristics
(V
CC
= +3.3V, |V
ID
| = 0.2V, V
CM
= +1.2V, T
A
= +25°C, f
IN
= 6.25MHz, Figure 5.)
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
MAX9396 toc02
SUPPLY CURRENT vs. TEMPERATURE
MAX9396 toc01
OUTPUT AMPLITUDE vs. FREQUENCY
700
600
OUTPUT AMPLITUDE (mV)
500
400
300
200
100
0
360
f
IN
= 100MHz
330
RISE/FALL TIME (ps)
300
270
240
210
t
F
180
65
SUPPLY CURRENT (mA)
V
CC
= +3.6V
60
V
CC
= +3.3V
55
50
45
40
-40
-15
-10
35
60
V
CC
= +3V
t
R
85
0
0.2
0.4
0.6
0.8
1.0
-40
-15
10
35
60
85
TEMPERATURE (°C)
FREQUENCY (GHz)
TEMPERATURE (°C)
PROPAGATION DELAY vs. TEMPERATURE
MAX9396 toc04
SINGLE-ENDED INPUT CURRENT
vs. TEMPERATURE
120
INPUT CURRENT (µA)
100
80
60
40
20
0
-20
V
IN_ _
= 0V
V
IN_ _
= V
CC
MAX9396 toc05
480
455
PROPAGATION DELAY (ps)
430
405
380
355
330
305
280
-40
-15
10
35
60
t
P
LH
t
P
HL
140
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
MAX9396 toc03
70
2:1 Multiplexer and 1:2 Demultiplexer
with Loopback
Pin Description
PIN
1, 2, 3,
30, 31, 32
4, 9, 20, 25
5
6
7
8, 13, 24, 29
10
11
NAME
N.C.
GND
ENB
OUTB
OUTB
V
CC
INB0
INB0
No Connection. Not internally connected.
Ground
Channel B Output Enable. Drive ENB high to enable the LVDS outputs for channel B. An internal
435kΩ resistor to GND pulls ENB low when unconnected.
Channel B LVDS Noninverting Output
Channel B LVDS Inverting Output
Power-Supply Input. Bypass each V
CC
to GND with a 0.1µF and 0.01µF ceramic capacitor. Install
both bypass capacitors as close as possible to the device, with the 0.01µF capacitor closest to the
device.
LVPECL/CML Inverting Input. An internal 68kΩ resistor to GND pulls the input low when unconnected.
LVPECL/CML Noninverting Input. An internal 68kΩ resistor to GND pulls the input low when
unconnected.
Loopback Select for Channel B Output. Connect LB_SELB to GND or leave unconnected to
reproduce the INB_ (INB_) differential inputs at OUTB (OUTB). Connect LB_SELB to V
CC
to loop back
the INA (INA) differential inputs to OUTB (OUTB). An internal 435kΩ resistor to GND pulls LB_SELB
low when unconnected.
LVPECL/CML Inverting Input. An internal 68kΩ resistor to GND pulls the input low when unconnected.
LVPECL/CML Noninverting Input. An internal 68kΩ resistor to GND pulls the input low when
unconnected.
Channel B Multiplexer Control Input. Selects the differential input to reproduce at the B channel
differential output. Connect BSEL to GND or leave unconnected to select the INB0 (INB0) set of
inputs. Connect BSEL to V
CC
to select the INB1 (INB1) set of inputs. An internal 435kΩ resistor to
GND pulls BSEL low when unconnected.
Channel A1 Output Enable. Drive ENA1 high to enable the A1 LVDS outputs. An internal 435kΩ
resistor to GND pulls the ENA1 low when unconnected.
Channel A1 LVDS Inverting Output
Channel A1 LVDS Noninverting Output
FUNCTION
MAX9396
12
LB_SELB
14
15
INB1
INB1
16
BSEL
17
18
19
ENA1
OUTA1
OUTA1
_______________________________________________________________________________________
5
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