DATA SHEET
SILICON POWER MOS FET
NE5500479A
3.5 V OPERATION SILICON RF POWER LDMOS FET
FOR 900 MHz 1 W TRANSMISSION AMPLIFIERS
DESCRIPTION
The NE5500479A is an N-channel silicon power MOS FET specially designed as the transmission power amplifier
for cellular handsets. Dies are manufactured using our NEWMOS technology (our 0.6
µ
m WSi gate laterally diffused
MOS FET) and housed in a surface mount package. The device can deliver 31.5 dBm output power with 62% power
added efficiency at 900 MHz as AMPS final output stage amplifier under the 3.5 V supply voltage. It also can deliver
35 dBm output power with 62% power added efficiency at 4.8 V, as GSM 900 class 4 final stage amplifiers.
FEATURES
• High output power
• High linear gain
• Surface mount package
• Single supply
: P
out
= 31.5 dBm TYP. (V
DS
= 3.5 V, I
Dset
= 300 mA, f = 900 MHz, P
in
= 20 dBm)
: G
L
= 15.0 dB TYP. (V
DS
= 3.5 V, I
Dset
= 300 mA, f = 900 MHz, P
in
= 10 dBm)
: 5.7
×
5.7
×
1.1 mm MAX.
: V
DS
= 3.0 to 8.0 V
• High power added efficiency :
η
add
= 62% TYP. (V
DS
= 3.5 V, I
Dset
= 300 mA, f = 900 MHz, P
in
= 20 dBm)
APPLICATIONS
• Analog cellular phones
• Digital cellular phones
• Others
: 3.5 V AMPS handsets
: 4.8 V GSM 900 class 4 handsets
: General purpose amplifiers for 800 to 1 000 MHz TDMA applications
ORDERING INFORMATION
Part Number
NE5500479A-T1
Package
79A
Marking
R4
Supplying Form
• 12 mm wide embossed taping
• Gate pin face the perforation side of the tape
• Qty 1 kpcs/reel
Remark
To order evaluation samples, contact your nearby sales office.
Part number for sample order: NE5500479A
Caution Observe precautions when handling because these devices are sensitive to electrostatic discharge.
The information in this document is subject to change without notice. Before using this document, please confirm that
this is the latest version.
Not all devices/types available in every country. Please check with local NEC Compound Semiconductor Devices
representative for availability and additional information.
Document No. PU10119EJ03V0DS (3rd edition)
Date Published July 2003 CP(K)
Printed in Japan
The mark
shows major revised points.
NEC Compound Semiconductor Devices 1999, 2003
NE5500479A
ABSOLUTE MAXIMUM RATINGS (T
A
= +25°C)
°
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Drain Current (Pulse Test)
Total Power Dissipation
Channel Temperature
Storage Temperature
Symbol
V
DS
V
GS
I
D
I
D
Note
P
tot
T
ch
T
stg
Ratings
20.0
5.0
1.0
2.0
10
125
−65
to +125
Unit
V
V
A
A
W
°C
°C
Note
Duty Cycle
≤
50%, T
on
≤
1 s
RECOMMENDED OPERATING CONDITIONS
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Input Power
Symbol
V
DS
V
GS
I
D
P
in
f = 900 MHz, V
DS
= 3.5 V
Test Conditions
MIN.
3.0
0
−
18
TYP.
3.5
2.0
600
20
MAX.
8.0
3.5
700
22
Unit
V
V
mA
dBm
ELECTRICAL CHARACTERISTICS (T
A
= +25°C)
°
Parameter
Gate to Source Leak Current
Drain to Source Leakage Current
(Zero Gate Voltage Drain Current)
Gate Threshold Voltage
Transconductance
Drain to Source Breakdown Voltage
Thermal Resistance
Linear Gain
Symbol
I
GSS
I
DSS
V
th
G
m
BV
DSS
R
th
G
L
Test Conditions
V
GSS
= 5.0 V
V
DSS
= 8.5 V
V
DS
= 4.8 V, I
D
= 1 mA
V
DS
= 4.8 V, I
D
= 600 mA
I
DSS
= 10
µ
A
Channel to Case
f = 900 MHz, P
in
= 10 dBm,
V
DS
= 3.5 V, I
Dset
= 300 mA,
Note
f = 900 MHz, P
in
= 20 dBm,
V
DS
= 3.5 V, I
Dset
= 300 mA,
Note
MIN.
−
−
1.0
−
20
−
−
30.5
−
55
TYP.
−
−
1.35
1.43
24
10
15.0
MAX.
100
100
2.0
−
−
−
−
−
−
−
Unit
nA
nA
V
S
V
°C/W
dB
Output Power
Operating Current
Power Added Efficiency
P
out
I
op
31.5
600
62
dBm
mA
%
η
add
Note
DC performance is 100% testing. RF performance is testing several samples per wafer.
Wafer rejection criteria for standard devices is 1 reject for several samples.
2
Data Sheet PU10119EJ03V0DS
NE5500479A
TYPICAL CHARACTERISTICS (T
A
= +25°C)
°
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
14.0
12.0
Drain Current I
D
(A)
SET DRAIN CURRENT vs.
GATE TO SOURCE VOLTAGE
10 000
V
DS
= 3.5 V
Set Drain Current I
Dset
(mA)
V
GS
= 10 V MAX.
Step = 1.0 V
10.0
8.0
6.0
4.0
2.0
0
2
4
6
8
10
12
14
16
1 000
100
10
1
1.0
1.5
2.0
2.5
3.0
Drain to Source Voltage V
DS
(V)
Gate to Source Voltage V
GS
(V)
OUTPUT POWER, DRAIN CURRENT
vs. INPUT POWER
35
Drain Efficiency
η
d
(%)
Power Added Efficiency
η
add
(%)
DRAIN EFFICIENCY, POWER ADDED
EFFICIENCY vs. INPUT POWER
1 250
100
V
DS
= 3.5 V
I
Dset
= 300 mA
f = 900 MHz
Output Power P
out
(dBm)
25
I
D
750
Drain Current I
D
(mA)
30
V
DS
= 3.5 V
I
Dset
= 300 mA
f = 900 MHz
P
out
1 000
η
d
η
add
50
20
500
15
250
0
30
10
0
5
10
15
20
25
0
5
10
15
20
25
30
Input Power P
in
(dBm)
Input Power P
in
(dBm)
OUTPUT POWER, DRAIN CURRENT
vs. GATE TO SOURCE VOLTAGE
32
V
DS
= 3.5 V
f = 900 MHz
P
in
= 20 dBm
1 250
P
out
Drain Current I
D
(mA)
DRAIN EFFICIENCY, POWER ADDED
EFFICIENCY vs. GATE TO SOURCE VOLTAGE
100
Drain Efficiency
η
d
(%)
Power Added Efficiency
η
add
(%)
Output Power P
out
(dBm)
31
1 000
V
DS
= 3.5 V
f = 900 MHz
P
in
= 20 dBm
η
d
η
add
50
30
750
29
I
D
500
28
250
0
4.0
27
0.0
1.0
2.0
3.0
0
1.0
2.0
3.0
4.0
Gate to Source Voltage V
GS
(V)
Gate to Source Voltage V
GS
(V)
Data Sheet PU10119EJ03V0DS
3
NE5500479A
OUTPUT POWER, DRAIN CURRENT
vs. INPUT POWER
35
DRAIN EFFICIENCY, POWER ADDED
EFFICIENCY vs. INPUT POWER
1 250
100
Output Power P
out
(dBm)
25
750
Drain Current I
D
(mA)
30
P
out
1 000
Drain Efficiency
η
d
(%)
Power Added Efficiency
η
add
(%)
V
DS
= 3.0 V
I
Dset
= 300 mA
f = 900 MHz
V
DS
= 3.0 V
I
Dset
= 300 mA
f = 900 MHz
η
d
η
add
50
20
I
D
15
500
250
0
30
10
0
5
10
15
20
25
0
5
10
15
20
25
30
Input Power P
in
(dBm)
Input Power P
in
(dBm)
OUTPUT POWER, DRAIN CURRENT
vs. GATE TO SOURCE VOLTAGE
31
V
DS
= 3.0 V
f = 900 MHz
P
in
= 20 dBm
1 250
P
out
DRAIN EFFICIENCY, POWER ADDED
EFFICIENCY vs. GATE TO SOURCE VOLTAGE
100
Output Power P
out
(dBm)
Drain Current I
D
(mA)
30
1 000
Drain Efficiency
η
d
(%)
Power Added Efficiency
η
add
(%)
V
DS
= 3.0 V
f = 900 MHz
P
in
= 20 dBm
η
d
η
add
50
29
750
28
I
D
27
500
250
0
4.0
26
0.0
1.0
2.0
3.0
0
1.0
2.0
3.0
4.0
Gate to Source Voltage V
GS
(V)
Gate to Source Voltage V
GS
(V)
Remark
The graphs indicate nominal characteristics.
4
Data Sheet PU10119EJ03V0DS
NE5500479A
S-PARAMETERS
S-parameters/Noise parameters are provided on the NEC Compound Semiconductor Devices Web site in a form
(S2P) that enables direct import to a microwave circuit simulator without keyboard input.
Click here to download S-parameters.
[RF and Microwave]
→
[Device Parameters]
URL http://www.csd-nec.com/
LARGE SIGNAL IMPEDANCE (V
DS
= 3.5 V, I
D
= 300 mA, P
in
= 20 dBm)
f (MHz)
900
Z
in
(Ω)
TBD
Z
OL
(Ω)
Note
TBD
Note
Z
OL
is the conjugate of optimum load impedance at given voltage, idling current, input power and frequency.
Data Sheet PU10119EJ03V0DS
5
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