19-1855 Rev 0; 11/00
+3.3V, 2.5Gbps Quad Transimpedance Amplifier
for System Interconnects
General Description
The MAX3825 is a quad transimpedance amplifier (TIA)
intended for 2.5Gbps system interconnect applications.
Each of the four channels converts a small photodiode
current to a measurable differential voltage with a tran-
simpedance gain of 3.7kΩ. The circuit features
460nA
RMS
of input-referred noise per channel corre-
sponding to an optical input sensitivity of -22.3dBm
(BER
≤
1
×
10
-14
). The quad transimpedance amplifier
has 20ps of deterministic jitter and a 2.4GHz small-sig-
nal bandwidth. The MAX3825 is optimized for use with
a quad PIN photodetector array with a standard fiber
pitch of 250µm.
The MAX3825 operates from a single +3.3V supply
over a 0°C to +85°C temperature range. With a +3.3V
supply, each channel dissipates 93mW of power. A DC
cancellation circuit on each channel provides a true dif-
ferential output swing over a wide range of input cur-
rents.
Each channel has an independent supply and ground
to allow all or any combination of channels to be con-
nected. This device is available in dice only.
Typical Operating Circuit appears at end of data sheet.
Features
o
o
o
o
o
o
o
o
o
Single +3.3V Supply
93mW per Channel Power Dissipation
460nA
RMS
Input-Referred Noise
20ps Deterministic Jitter
2.4GHz Small-Signal Bandwidth
No External Compensation
40dB Power-Supply Rejection Ratio
Compact Die with 250µm Channel Pitch
100Ω Differential Output Impedance
MAX3825
Ordering Information
PART
MAX3825U/D
TEMP. RANGE
0°C to +85°C
PIN-PACKAGE
Dice*
*Dice
are designed to operate with a 0°C to +120°C junction
temperature, but are tested and guaranteed only at T
A
= +25°C.
Applications
System Interconnects
SDH/SONET
Backplanes
Dense Digital Cross-
Connects
ATM Switching
Networks
High-Speed Parallel
Optical Links
Chip Topography/Pad Configuration
V
CCO1
OUT1+ OUT1- V
CCO1
V
CCO2
OUT2+ OUT2- V
CCO2
V
CCO3
OUT3+ OUT3- V
CCO3
V
CCO4
OUT4+ OUT4-V
CCO4
N.C.
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GNDO1
37
20
GNDO4
GNDO2
GNDF
38
39
19
18
17
16
15
14
GNDO3
ENABLE
GNDI2
VCCI2
VCCI1
GNDI1
V
CCFILT
40
41
42
43
44
1
N.C.
2
3
4
IN1
5
6
7
8
9
10
11
12
N.C.
13
N.C.
GNDI3
VCCI3
VCCI4
GNDI4
N.C. FILTER
FILT1 IN2 FILT2 IN3 FILT3 IN4 FILT4
________________________________________________________________
Maxim Integrated Products
1
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+3.3V, 2.5Gbps Quad Transimpedance Amplifier
for System Interconnects
MAX3825
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
V
CCO1
, V
CCO2
, V
CCO3
, V
CCO4
,
V
CCI1
, V
CCI2
, V
CCI3
, V
CCI4
, V
CCFILT
...............-0.5V to +6.0V
Input Current: IN1, IN2, IN3, IN4...........................-4mA to +4mA
FILTER Current..................................................-24mA to +24mA
Filter Current: FILT1, FILT2, FILT3, FILT4 .............-6mA to +6mA
Output Voltage OUT1±, OUT2±,
OUT3±, OUT4±............................(V
CC
- 1.5V) to (V
CC
+ 0.5V)
ENABLE
Voltage.........................................-0.5V to (V
CC
+ 0.5V)
Operating Temperature Range (T
A
)........................0°C to +85°C
Storage Temperature Range .............................-55°C to +150°C
Operating Junction Temperature (T
J
)................-55°C to +150°C
Processing Temperature..................................................+400°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.14V to +3.6V, T
A
= 0°C to +85°C. Typical values are at +3.3V, T
A
= +25°C, unless otherwise noted.)
MIN
TYP
PARAMETER
SYMBOL
CONDITIONS
Single channel
Supply Current
Input Bias Voltage
DC Input Overload
Transimpedance
Filter Resistor RFILTER
Filter Resistors RFILT1–4
Single-Ended Output Impedance
Transimpedance Linear Range
Maximum Differential Output
Range
Output Offset Voltage
Output Common Mode Voltage
V
offset
Z
21
R
FILTER
R
FILT_
R
O
(Note 1)
I
IN
= 2mAp-p
I
IN
= 10µAp-p
50Ω loads to V
CC
43
50
230
-5
V
CC
- 0.09
340
480
+5
10µAp-p, 100
Ω
differential load
I
CC
Dual channel
Quad channel
I
IN
= 0
1.7
3.0
3.7
180
720
50
57
4.5
28
56
112
0.89
MAX
40
80
160
0.99
mA
V
mA
kΩ
Ω
Ω
Ω
µAp-p
mVp-p
mV
V
UNITS
Note 1:
Gain at 50µAp-p is within 10% of the small signal gain.
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.14V to +3.6V, T
A
= 0°C to +85°C. Typical values are at +3.3V, T
A
= +25°C, unless otherwise noted. Total source capaci-
tance = 0.7pF.) (Note 2)
PARAMETER
AC Input Overload
Input Referred Noise
Low-Frequency Cutoff
Deterministic Jitter (Note 5)
Power-Supply Rejection Ratio
Small-Signal Bandwidth
Maximum Skew (Note 7)
DJ
PSRR
BW
Any two channels within a chip
I
N
(Note 4)
I
IN
> 100µAp-p
(Note 6)
SYMBOL
(Note 3)
CONDITIONS
MIN
2
460
60
20
40
2.4
50
600
100
45
TYP
MAX
UNITS
mAp-p
nA
rms
kHz
ps
dB
GHz
ps
2
_______________________________________________________________________________________
+3.3V, 2.5Gbps Quad Transimpedance Amplifier
for System Interconnects
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.14V to +3.6V, T
A
= 0°C to +85°C. Typical values are at +3.3V, T
A
= +25°C, unless otherwise noted. Total source capaci-
tance = 0.7pF.) (Note 2)
AC characteristics are guaranteed by design and characterization.
The maximum input current is specified with output deterministic jitter
≤
45ps.
No external compensation capacitors are used. Measured with I
IN
= 30µA
avg
.
Deterministic jitter is the arithmetic sum of pattern-dependent jitter and pulse width distortion. Measured with a 2
13
-1 PRBS
with 100 consecutive 0s and 100 consecutive 1s applied to a single channel. See
Typical Operating Characteristics.
Note 6:
PSRR = -20log(∆V
OUT
/ V
noise(on VCC)
), f
≤
2MHz. Measured by applying DC current = 30µA, and applying 100mVp-p signal
at power supply.
Note 7:
Measured by applying the same input signal to all channels. Skew measurements are made at the 50% point of the transition.
Note 2:
Note 3:
Note 4:
Note 5:
MAX3825
Typical Operating Characteristics
(V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
DETERMINISTIC JITTER
vs. INPUT AMPLITUDE
MAX3825 toc01
FREQUENCY RESPONSE
75
50
45
PEAK-TO-PEAK JITTER (ps)
40
35
30
25
20
15
10
5
50
1
10
100
FREQUENCY (MHz)
1000
10,000
0
0
INPUT-REFERRED RMS NOISE CURRENT
vs. DC INPUT CURRENT
MAX3825 toc02
MAX3825 toc03
1400
INPUT-REFERRED NOISE (nA
RMS
)
1200
1000
800
C
IN
= 0.7pF
600
400
200
0
70
TRANSIMPEDANCE (dB)
65
60
55
400
800
1200
1600
2000
10
100
DC INPUT CURRENT (µA)
1000
INPUT CURRENT AMPLITUDE (µAp-p)
DIFFERENTIAL OUTPUT AMPLITUDE
vs. TEMPERATURE
MAX3825 toc04
DC TRANSFER FUNCTION
DIFFERENTIAL OUTPUT VOLTAGE (mVp-p)
MAX3825 toc05
410
DIFFERENTIAL OUTPUT AMPLITUDE (mpVp-p)
390
370
350
330
310
290
270
250
INPUT = 2mAp-p
VCC = +3.6V
200
100
VCC = +3.14V
0
-100
-200
-15
10
35
60
85
-100
-50
0
50
100
AMBIENT TEMPERATURE (°C)
INPUT CURRENT (µA)
_______________________________________________________________________________________
3
+3.3V, 2.5Gbps Quad Transimpedance Amplifier
for System Interconnects
MAX3825
Typical Operating Characteristics (continued)
(V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
ELECTRICAL EYE DIAGRAM
INPUT = 2mAp-p, 2.5Gbps, 2
13
- 1 PRBS
MAX3825 toc06
ELECTRICAL EYE DIAGRAM
INPUT = 20µAp-p, 2.5Gbps, 2
13
- 1 PRBS
MAX3825 toc07
10mV/div
10mV/div
RL = 100Ω DIFFERENTIAL
50ps/div
RL = 100Ω DIFFERENTIAL
50ps/div
Pad Description
PAD
1, 2, 12, 13
3
4, 6, 8, 10
5, 7, 9, 11
14, 17, 40, 43
15, 16, 41, 42
18
20, 19, 38, 37
21, 24
22, 26, 30, 34
23, 27, 31, 35
25, 28
29, 32
33, 36
39
44
NAME
N.C.
FILTER
IN1 to IN4
FILT1 to FILT4
GNDI4 to GNDI1
V
CCI4
to V
CCI1
ENABLE
GNDO4 to GNDO1
V
CCO4
OUT4- to OUT1-
OUT4+ to OUT1+
V
CCO3
V
CCO2
V
CCO1
GNDF
V
CCFILT
FUNCTION
No Connection. Leave open and unconnected.
Connection to internal 180Ω Filter Resistor to V
CCFILT
for Photodiode Array Cathode Bias
Signal Inputs. Channel 1 to channel 4 signal inputs.
Filter Connections. Channel 1 to channel 4 connection to internal filter resistors (720Ω to
V
CCFILT
).
Input Stage Ground Connections. Channel 4 to channel 1 input stage ground.
Input Stage Supply Connections. Channel 4 to channel 1 input stage positive supply.
DC Feedback Disable. Disables DC feedback of all four channels when connected to the
positive supply (V
CC
). Left unconnected for normal operation.
Output Stage Ground Connections. Channel 4 to channel 1 output stage ground.
Channel 4 Output Stage Positive Supply
Inverting Outputs. Channel 4 to channel 1 negative outputs.
Noninverting Outputs. Channel 4 to channel 1 positive outputs.
Channel 3 Output Stage Positive Supply
Channel 2 Output Stage Positive Supply
Channel 1 Output Stage Positive Supply
Ground Connection for the Filters. Filter grounds.
Power Supply Connection for Filter Resistor
4
_______________________________________________________________________________________
+3.3V, 2.5Gbps Quad Transimpedance Amplifier
for System Interconnects
Functional Diagram
V
CC
FILT
720Ω
D2
V
CCO_
D1
R1
50Ω
R
F
= 1.3kΩ
VCCI_
V
CCO_
IN_
Q1
C1
GNDI_
R5
VCCI_
Q3
PARAPHASE
AMP
R2
50Ω
OUT_-
Q2
FILT_
MAX3825
OUT_+
Q5
REFERENCE
AMP
R4
R3
GNDI_
DC
CANCELLATION
AMP
Q4
GNDI_
MAX3825
ENABLE
GNDO_
Figure 1. Functional Diagram for One Channel of the MAX3825
Detailed Description
The MAX3825 quad TIA circuit is designed for 2.5Gbps
SONET/SDH applications. It comprises a transimped-
ance amplifier, a paraphase amplifier with CML out-
puts, and a DC cancellation loop to reduce pulse-width
distortion (Figure 1).
DC Cancellation Loop
The DC cancellation loop removes the DC component
of the input signal by using low-frequency feedback.
This feature centers the signal within the MAX3825’s
dynamic range, reducing pulse-width distortion.
The output of the paraphrase amplifier is sensed through
resistors R3 and R4 and then filtered, amplified, and fed
back to the base of transistor Q4. The transistor draws
the DC component of the input signal away from the
transimpedance amplifier’s summing node.
The MAX3825 DC cancellation loop is internally com-
pensated and does not require external capacitors in
most 2.5Gbps applications. The DC cancellation loop
for all channels can be disabled by connecting
ENABLE
to the positive supply (V
CC
).
ENABLE
is inter-
5
Transimpedance Amplifier
The signal current at IN_ flows into the summing node
of a high-gain amplifier. Shunt feedback through R
F
converts this current to a voltage with a gain of 1300Ω.
Diodes D1 and D2 clamp the output voltage for large
input currents. GNDI_ is a direct connection to the emit-
ter of the input transistor and must be connected
directly to the photodetector AC ground return for best
performance.
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