19-3286; Rev 0; 5/04
Low-Jitter 106.25MHz/212.5MHz Fibre-Channel
Clock Generator
General Description
The MAX3610 is a low-jitter, high-performance, dual-rate
clock generator optimized for 1Gbps/2Gbps/4Gbps
Fibre-Channel applications. When connected with an
external AT-cut crystal, the device generates a precision
clock output by integrating a crystal oscillator with
Maxim’s low-noise phase-locked loop (PLL) providing a
low-cost solution. By coupling Maxim’s low-noise PLL
design featuring a low-jitter generation VCO with an
inexpensive fundamental mode crystal, the MAX3610
provides the optimum combination of low cost, flexibility,
and high performance.
The MAX3610 output frequency is selectable. When
using a 26.5625MHz crystal, the output clock rate can
be set to either 106.25MHz or 212.5MHz. When operat-
ing at 106.25MHz, the typical phase jitter is 0.7ps
RMS
from 12kHz to 20MHz. The MAX3610A has low-voltage
positive-emitter-coupled logic (LVPECL) clock output
drivers. The MAX3610B has low-voltage differential-sig-
nal (LVDS) clock output drivers. The MAX3610 output
drivers can also be disabled.
The MAX3610 operates from a single +3.3V supply.
The PECL version typically consumes 165mW, while the
LVDS version typically consumes 174mW. Both devices
are available in die form and have a 0°C to +85°C oper-
ating temperature range.
Features
♦
Clock Output Frequencies: 106.25MHz or
212.5MHz
♦
Phase Jitter: 0.7ps
RMS
♦
LVPECL or LVDS Output
♦
Excellent Power-Supply Noise Rejection
♦
Supply Current: 50mA at +3.3V Supply (LVPECL)
53mA at +3.3V Supply (LVDS)
♦
0°C to +85°C Temperature Range
♦
Optional Output Disable
MAX3610
Ordering Information
PART
MAX3610AU/D
MAX3610BU/D
TEMP RANGE
0°C to +85°C
0°C to +85°C
PIN-
PACKAGE
Die
Die
OUTPUTS
LVPECL
LVDS
Applications
Fibre-Channel Hard Disk Drives
Host Bus Adapters
Raid Controllers
Fibre-Channel Switches
Dice are designed to operate from 0°C to +85°C, but are tested
and guaranteed only at T
A
= +25°C.
Typical Operating Circuits
+3.3V
+3.3V
0.1µF
0.1µF
OE
AT CUT
CRYSTAL
X1
V
CC
FREQSET
+3.3V
AT CUT
CRYSTAL
OE
V
CC
FREQSET
+3.3V
MAX3610A
OUT+
DEVICE WITH
LVPECL INPUTS
X1
MAX3610B
OUT+
100Ω
DEVICE WITH
LVDS INPUTS
X2
GND
OUT-
50Ω
50Ω
X2
GND
OUT-
OPERATING AT 106.25MHz
LVPECL OUTPUTS
V
CC
-2V
OPERATING AT 106.25MHz
LVDS OUTPUTS
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Low-Jitter 106.25MHz/212.5MHz Fibre-Channel
Clock Generator
MAX3610
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ......................................................-0.5V to +5.0V
Voltage at FREQSET, OE............................-0.5V to (V
CC
+ 0.5V)
Voltage at X1 .........................................................-0.5V to +0.8V
Voltage at X2 .....................................................................0 to 2V
PECL Output Current ..........................................................56mA
LVDS Output Voltage .................................-0.5V to (V
CC
+ 0.5V)
Operating Temperature Range...............................0°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Processing Temperature..................................................+400°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= 0°C to +85°C. Typical values are at V
CC
= +3.3V and T
A
= +25°C, unless otherwise noted.) (Note 1 )
PARAMETER
Supply Current
SYMBOL
I
CC
(Note 2)
CONDITIONS
LVPECL
LVDS
V
CC
-
1.025
V
CC
-
1.81
MIN
TYP
50
53
MAX
65
67
V
CC
-
0.88
V
CC
-
1.62
1.475
0.925
250
400
25
UNITS
mA
LVPECL OUTPUT SPECIFICATIONS (Note 3)
Output High Voltage
Output Low Voltage
V
OH
V
OL
0°C to +85°C
0°C to +85°C
V
V
LVDS OUTPUT SPECIFICATIONS (Figure 1)
LVDS Output High Voltage
LVDS Output Low Voltage
LVDS Differential Output Voltage
LVDS Change in Magnitude of
Differential Output for
Complementary States
LVDS Offset Output Voltage
(Output Common-Mode Voltage)
LVDS Change in Magnitude of
Output Offset Voltage for
Complementary States
LVDS Differential Output
Impedance
LVDS Output Current
TTL Control Input-Voltage High
TTL Control Input-Voltage Low
Input Current (Input High)
Input Current (Input Low)
CLOCK OUTPUT SPECIFICATIONS
Clock Output Frequency
Crystal Oscillation Circuit Input
Capacitance
FREQSET = TTL High, VCC, or NC
FREQSET = TTL Low or GND
106.25
212.5
12
MHz
pF
V
IH
V
IL
I
IH
I
IL
-10
-50
Outputs shorted together
2
0.8
+10
+10
CONTROL INPUT SPECIFICATIONS (FREQSET, OE)
V
V
µA
µA
V
OH
V
OL
|V
OD
|
∆|V
OD
|
V
V
mV
mV
V
OS
∆|V
OS
|
1.125
1.275
V
25
mV
Ω
mA
80
100
140
12
2
_______________________________________________________________________________________
Low-Jitter 106.25MHz/212.5MHz Fibre-Channel
Clock Generator
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= 0°C to +85°C. Typical values are at V
CC
= +3.3V and T
A
= +25°C, unless otherwise noted.) (Note 1 )
PARAMETER
Phase Jitter
Accumulated Deterministic Jitter
Due to Reference Spurs
10kHz
Accumulated Deterministic Jitter
Due to Power-Supply Noise
(Note 4)
100kHz
200kHz
1MHz
Clock-Output Edge Speeds
Clock-Output Duty Cycle
Oscillation Startup Time
(Note 5)
100Hz
1kHz
Clock-Output SSB Phase Noise
Measured at 106.25MHz
10kHz
100kHz
1MHz
10MHz
-90
-112
-115
-123
-142
-147
dBc/Hz
t
R
, t
F
20% to 80%
LVPECL outputs
LVDS outputs
250
200
49
SYMBOL
PJ
RMS
CONDITIONS
12kHz to 20MHz
MIN
TYP
0.7
3.0
3.0
27
15
7
600
600
51
5
ps
%
ms
69
43
ps
P-P
MAX
1.0
UNITS
ps
RMS
ps
P-P
MAX3610
Note 1:
AC parameters are guaranteed by design and characterization.
Note 2:
Outputs are enabled and unloaded.
Note 3:
When LVPECL output is disabled to high impedance, the typical output off-current is <100µA for nominal LVPECL signal
levels at the output.
Note 4:
Measured with 50mV
P-P
sinusoidal signal on the supply, from 10kHz to 1MHz.
Note 5:
Including oscillator startup time and PLL acquisition time, measured after V
CC
reaches 3.0V from power on.
OUT+
D
OUT-
V
OUT+
SINGLE-ENDED OUTPUT
V
OUT-
|V
OD
|
V
OH
V
OS
V
OL
R
L
= 100Ω
V
V
OD
+V
OD
DIFFERENTIAL OUTPUT
0V (DIFF)
0V
-V
OD
V
ODP-P
= V
OUT+
- V
OUT-
Figure
1. LVDS Swing Definitions
_______________________________________________________________________________________
3
Low-Jitter 106.25MHz/212.5MHz Fibre-Channel
Clock Generator
MAX3610
Typical Operating Characteristics
(V
CC
= 3.3V, T
A
= +25°C, unless otherwise noted.)
POWER-SUPPLY CURRENT
vs. TEMPERATURE
MAX3610 toc01
OUTPUT DETERMINISTIC JITTER DUE TO
POWER-SUPPLY NOISE vs. FREQUENCY
MAX3610 toc02
OUTPUT DETERMINISTIC JITTER DUE TO
POWER-SUPPLY NOISE vs. SUPPLY VOLTAGE
OUTPUT DETERMINISTIC JITTER (ps
P-P
)
45
40
35
30
25
20
15
10
5
0
3.0
200kHz SUPPLY NOISE
3.1
3.2
3.3
3.4
3.5
3.6
100kHz SUPPLY NOISE
212.5MHz CLOCK OUTPUT
50mV
P-P
SUPPLY NOISE
VOLTAGE AMPLITUDE
MAX3610 toc03
80
75
SUPPLY CURRENT (mA)
70
65
60
55
50
LVPECL DEVICE
45
40
0
10
20
30
40
50
60
70
80
SUPPLY VOLTAGE (V)
LVDS DEVICE
80
OUTPUT DETERMINISTIC JITTER (ps
P-P
)
70
60
50
40
30
20
10
0
1
10
100
100mV
P-P
NOISE
50mV
P-P
NOISE
50
1000
FREQUENCY OF POWER-SUPPLY NOISE VOLTAGE (kHz)
SUPPLY VOLTAGE LEVEL (V)
Pin Description
PAD
1, 2, 3, 6, 7, 9,
10, 11, 15–18
4
5
8
12
13
14
19
20
NAME
N.C.
X1
X2
OE
OUT-
GND
OUT+
FREQSET
V
CC
No Connection
Crystal Oscillator Input
Crystal Oscillator Output
Output Enable. On-chip pullup resistor. Connect OE to logic-high, V
CC
, or leave open to enable the
output clock. Connect OE to logic-low or GND to disable the output clock. LVPECL output clock is set
to high impedance when disabled. LVDS output clock is latched to a differential high when disabled.
Negative Clock Output, LVPECL or LVDS
Ground
Positive Clock Output, LVPECL or LVDS
Output Frequency Select. On-chip pullup resistor. Connect FREQSET to logic-high, V
CC
, or leave open
to set the output clock rate to 106.25MHz. Connect FREQSET to logic-low or GND to set the output
clock rate to 212.5MHz.
+3.3V Supply
FUNCTION
4
_______________________________________________________________________________________
Low-Jitter 106.25MHz/212.5MHz Fibre-Channel
Clock Generator
MAX3610
Functional Diagram
FREQSET
MAX3610A
MAX3610B
X1
OSCILLATOR
GAIN CIRCUIT
X2
PFD
LOOP
FILTER
VCO
COUNTER
M
OUTPUT
BUFFER
OUT+
OUT-
PLL
COUNTER
N
OE
Figure 2. Functional Diagram
Detailed Description
The MAX3610 contains all of the blocks needed to form a
precision Fibre-Channel clock except for the external
crystal, which must be supplied separately. Figure 2
shows a functional block diagram of the MAX3610. The
MAX3610 consists of a crystal oscillator, a low-noise PLL,
selectable clock-divider circuitry, and an output buffer.
Optimal performance is achieved by integrating the
crystal oscillator with a low-noise PLL. The PLL consists
of a digital phase/frequency detector (PFD) and low-jit-
ter generation VCO. The VCO signal is scaled by clock-
divider circuitry and applied to the output buffer. The
MAX3610 is available with either LVPECL or LVDS out-
put buffers (see the
Ordering Information).
scaling the VCO output frequency. Clock-divider circuit
N applies a scaled version of the output clock signal to
the PFD. A TTL low applied to FREQSET, sets clock-
divider M ratio to 16, and clock-divider N ratio to 8. With
FREQSET pulled low, the output clock rate is
212.5MHz. A TTL high applied to FREQSET sets the
clock-divider M ratio to 32, and clock-divider N ratio to
4. With FREQSET pulled high, the output clock rate is
106.25MHz.
Output Drivers
The MAX3610 is available with either LVPECL
(MAX3610A) or LVDS (MAX3610B) output buffers.
When not needed, the output buffers can be disabled.
When disabled, the LVPECL output buffer goes to a
high-impedance state. However, the LVDS outputs go
to a differential 1 (OUT+ latched high and OUT- latched
low) when the outputs are disabled.
Oscillator Gain Circuit
The input capacitance of the oscillator gain circuit is
trimmed to 12pF of capacitance and produces oscilla-
tions at 26.5625MHz when interfaced with the appropri-
ate external crystal (see Table 1 for the external crystal
specifications).
Design Procedure
Crystal Resonator Specifications
The MAX3610 is designed to operate with an inexpen-
sive fundamental mode crystal. Table 1 specifies the
characteristics of a typical crystal to be interfaced with
the MAX3610.
PLL
The PLL generates a 1.7GHz high-speed clock signal
based on the 26.5625MHz crystal oscillator output.
Clock-divider circuit M generates the output clock by
_______________________________________________________________________________________
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
