LTC1272
12-Bit, 3µs, 250kHz
Sampling A/D Converter
FEATURES
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DESCRIPTIO
AD7572 Pinout
12-Bit Resolution
3µs and 8µs Conversion Times
On-Chip Sample-and-Hold
Up to 250kHz Sample Rates
5V Single Supply Operation
No Negative Supply Required
On-Chip 25ppm/°C Reference
75mW (Typ) Power Consumption
24-Pin Narrow DIP and SOL Packages
ESD Protected on All Pins
The LTC1272 is a 3µs, 12-bit, successive approximation
sampling A/D converter. It has the same pinout as the
industry standard AD7572 and offers faster conversion
time, on-chip sample-and-hold, and single supply opera-
tion. It uses LTBiCMOS
TM
switched-capacitor technology to
combine a high speed 12-bit ADC with a fast, accurate
sample-and-hold and a precision reference.
The LTC1272 operates with a single 5V supply but can also
accept the 5V/–15V supplies required by the AD7572 (Pin
23, the negative supply pin of the AD7572, is not connected
on the LTC1272). The LTC1272 has the same 0V to 5V input
range as the AD7572 but, to achieve single supply opera-
tion, it provides a 2.42V reference output instead of the
– 5.25V of the AD7572. It plugs in for the AD7572 if the
reference capacitor polarity is reversed and a 1µs sample-
and-hold acquisition time is allowed between conversions.
The output data can be read as a 12-bit word or as two
8-bit bytes. This allows easy interface to both 8-bit and
higher processors. The LTC1272 can be used with a
crystal or an external clock and comes in speed grades of
3ms and 8ms.
APPLICATIO S
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High Speed Data Acquisition
Digital Signal Processing (DSP)
Multiplexed Data Acquisition Systems
Single Supply Systems
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
LTBiCMOS is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATIO
LTC1272
2.42V
V
REF
OUTPUT
ANALOG INPUT
(0V TO 5V)
A
IN
V
REF
10µF
AGND
D11 (MSB)
D10
D9
D8
D7
8 OR 12-BIT
PARALLEL
BUS
D6
D5
D4
DGND
Single 5V Supply, 3µs, 12-Bit Sampling ADC
5V
1024 Point FFT, f
S
= 250kHz, f
IN
= 10kHz
0
V
DD
NC
BUSY
CS
RD
HBEN
CLK OUT
CLK IN
D0/8
D1/9
D2/10
D3/11
10
µ
F
+
0.1µF
+
–20
0.1
µ
F
–40
µ
P
CONTROL
LINES
AMPLITUDE (dB)
–60
–80
–100
–120
–140
0
20
40
60
80
100
120
LTC1272 • TA02
LTC1272 • TA01
U
S = 72.1
(N+D)
FREQUENCY (kHz)
1272fb
U
U
1
LTC1272
ABSOLUTE
(Notes 1 and 2)
AXI U
RATI GS
Operating Temperature Range
LTC1272-XAC, CC ................................. 0°C to 70°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
Supply Voltage (V
DD
) ................................................. 6V
Analog Input Voltage (Note 3) ...................– 0.3V to 15V
Digital Input Voltage ..................................– 0.3V to 12V
Digital Output Voltage .................... – 0.3V to V
DD
+ 0.3V
Power Dissipation.............................................. 500mW
PACKAGE/ORDER I FOR ATIO
TOP VIEW
A
IN
V
REF
AGND
(MSB) D11
D10
D9
D8
D7
D6
1
2
3
4
5
6
7
8
9
24 V
DD
23 NC
22 BUSY
21 CS
20 RD
19 HBEN
18 CLK OUT
17 CLK IN
16 D0/8
15 D1/9
14 D2/10
13 D3/11
N PACKAGE
24-LEAD PDIP
T
JMAX
= 110°C,
θ
JA
= 100°C/W
TOP VIEW
A
IN
V
REF
AGND
(MSB) D11
D10
D9
D8
D7
D6
1
2
3
4
5
6
7
8
9
24 V
DD
23 NC
22 BUSY
21 CS
20 RD
19 HBEN
18 CLK OUT
17 CLK IN
16 D0/8
15 D1/9
14 D2/10
13 D3/11
D5 10
D4 11
DGND 12
D5 10
D4 11
DGND 12
SW PACKAGE
24-LEAD PLASTIC SO WIDE
T
JMAX
= 110°C,
θ
JA
= 130°C/W
Order Options
Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking:
http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
CO VERTER CHARACTERISTICS
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
(Note 5)
CONDITIONS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. With Internal Reference (Note 4)
LTC1272-XA
MIN
●
●
●
●
Gain Error
Full-Scale Tempco
I
OUT
(Reference) = 0
●
2
U
U
W
W W
U
W
ORDER PART NUMBER
CONVERSION
TIME = 3µs
LTC1272-3ACN
LTC1272-3CCN
CONVERSION
TIME = 8µs
LTC1272-8ACN
LTC1272-8CCN
SW PACKAGE ONLY
LTC1272-3ACSW
LTC1272-3CCSW
LTC1272-8ACSW
LTC1272-8CCSW
U
LTC1272-XC
MAX
±1/2
±1
±3
±4
±10
MIN
12
±1
±1
±4
±6
±15
±10
±45
TYP
MAX
UNITS
Bits
LSB
LSB
LSB
LSB
LSB
ppm/°C
TYP
12
±5
±25
1272fb
LTC1272
I TER AL REFERE CE CHARACTERISTICS
PARAMETER
V
REF
Output Voltage (Note 6)
V
REF
Output Tempco
V
REF
Line Regulation
CONDITIONS
I
OUT
= 0
I
OUT
= 0
4.75V
≤
V
DD
≤
5.25V, I
OUT
= 0
●
The
●
denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at T
A
= 25°C. (Note 4)
LTC1272-XA
MIN
TYP
MAX
2.400
2.420
5
0.01
2
2.440
25
LTC1272-XC
MIN
TYP
MAX
2.400
2.420
10
0.01
2
2.440
45
UNITS
V
ppm/°C
LSB/V
LSB/mA
V
REF
Load Regulation (Sourcing Current) 0
≤ ⎢I
OUT
⎢ ≤
1mA
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
SYMBOL
V
IH
V
IL
I
IN
V
OH
V
OL
I
OZ
C
OZ
I
SOURCE
I
SINK
I
DD
P
D
PARAMETER
High Level Input Voltage CS, RD, HBEN, CLK IN
Low Level Input Voltage CS, RD, HBEN, CLK IN
Input Current CS, RD, HBEN
Input Current CLK IN
High Level Output Voltage All Logic Outputs
Low Level Output Voltage All Logic Outputs
High-Z Output Leakage D11-D0/8
High-Z Output Capacitance (Note 7)
Output Source Current
Output Sink Current
Positive Supply Current
Power Dissipation
V
OUT
= 0V
V
OUT
= V
DD
CS = RD = V
DD
, A
IN
= 5V
CONDITIONS
V
DD
= 5.25V
V
DD
= 4.75V
V
IN
= 0V to V
DD
V
IN
= 0V to V
DD
V
DD
= 4.75V
I
OUT
= – 10µA
I
OUT
= – 200µA
V
DD
= 4.75V, I
OUT
= 1.6mA
V
OUT
= 0V to V
DD
The
●
denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at T
A
= 25°C. (Note 4)
LTC1272-XA/C
MIN
TYP
MAX
●
●
●
●
DY A IC ACCURACY
SYMBOL
S/(N + D)
THD
PARAMETER
Signal-to-Noise Plus Distortion Ratio
Total Harmonic Distortion (Up to 5th Harmonic)
Peak Harmonic or Spurious Noise
The
●
I
A ALOG
at T
PUT
(Note 4) denotes the specifications which apply over the full operating temperature range, otherwise
= 25°C.
specifications are
A
SYMBOL
V
IN
I
IN
C
IN
t
ACQ
PARAMETER
Input Voltage Range
Input Current
Input Capacitance
Sample-and-Hold Acquisition Time
U
U
U
W U
U
U
U
UNITS
V
V
µA
µA
V
V
2.4
0.8
±10
±20
4.7
4.0
0.4
±10
15
– 10
10
●
●
●
●
V
µA
pF
mA
mA
●
15
75
30
mA
mW
(Note 4) f
SAMPLE
= 250kHz (LTC1272-3), 166kHz (LTC1272-5), 111kHz (LTC1272-8)
CONDITIONS
10kHz Input Signal
10kHz Input Signal
10kHz Input Signal
LTC1272-XA/C
MIN
TYP
MAX
72
– 82
– 82
UNITS
dB
dB
dB
CONDITIONS
4.75V
≤
V
DD
≤
5.25V
●
●
LTC1272-XA/B/C
MIN
TYP
MAX
0
50
●
UNITS
V
mA
pF
µs
5
3.5
0.45
1
1272fb
3
LTC1272
The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 8)
SYMBOL
t
1
t
2
t
3
PARAMETER
CS to RD Setup Time
RD to BUSY Delay
Data Access Time After RD
↓
C
L
= 50pF
COM Grade
C
L
= 20pF
COM Grade
C
L
= 100pF
COM Grade
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
CONV
RD Pulse Width
COM Grade
CS to RD Hold Time
Data Setup Time After BUSY
COM Grade
Bus Relinquish Time
COM Grade
HBEN to RD Setup Time
HBEN to RD Hold Time
Delay Between RD Operations
Delay Between Conversions
Aperture Delay of Sample and Hold
CLK to BUSY Delay
COM Grade
Conversion Time
●
●
●
●
●
●
●
●
●
TI I G CHARACTERISTICS
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
All voltage values are with respect to ground with DGND and
AGND wired together, unless otherwise noted.
Note 3:
When the analog input voltage is taken below ground it will be
clamped by an internal diode. This product can handle, with no external
diode, input currents of greater than 60mA below ground without latch-up.
Note 4:
V
DD
= 5V, f
CLK
= 4MHz for LTC1272-3, and 1.6MHz for
LTC1272-8, t
r
= t
f
= 5ns unless otherwise specified. For best analog
performance, the LTC1272 clock should be synchronized to the RD and
CS control inputs with at least 40ns separating convert start from the
nearest clock edge.
4
UW
CONDITIONS
●
●
LTC1272-XA/C
MIN
TYP
MAX
0
80
50
●
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
190
230
90
110
125
150
70
●
t
3
t
3
0
40
20
20
0
0
200
1
25
80
12
170
220
13
30
70
90
75
85
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
CLK
CYCLES
Jitter < 50ps
Note 5:
Linearity error is specified between the actual end points of the
A/D transfer curve.
Note 6:
The LTC1272 has the same 0V to 5V input range as the AD7572
but, to achieve single supply operation, it provides a 2.42V reference
output instead of the –5.25V of the AD7572. This requires that the polarity
of the reference bypass capacitor be reversed when plugging an LTC1272
into an AD7572 socket.
Note 7:
Guaranteed by design, not subject to test.
Note 8:
V
DD
= 5V. Timing specifications are sample tested at 25°C to
ensure compliance. All input control signals are specified with t
r
= t
f
= 5ns
(10% to 90% of 5V) and timed from a voltage level of 1.6V. See Figures 13
through 17.
1272fb
LTC1272
PI FU CTI
A
IN
(Pin 1):
Analog Input, 0V to 5V Unipolar Input.
V
REF
(Pin 2):
2.42V Reference Output. When plugging into
an AD7572 socket, reverse the reference bypass capacitor
polarity and short the 10Ω series resistor.
AGND (Pin 3):
Analog Ground.
D11 to D4 (Pins 4-11):
Three-State Data Outputs.
DGND (Pin 12):
Digital Ground.
D3/11 to D0/8 (Pins 13-16):
Three-State Data Outputs.
CLK IN (Pin 17):
Clock Input. An external TTL/CMOS
compatible clock may be applied to this pin or a crystal can
be connected between CLK IN and CLK OUT.
CLK OUT (Pin 18):
Clock Output. An inverted CLK IN signal
appears at this pin.
Data Bus Output, CS and RD = LOW
Pin 4
MNEMONIC*
HBEN = LOW
HBEN = HIGH
D11
DB11
DB11
Pin 5
D10
DB10
DB10
Pin 6
D9
DB9
DB9
Pin 7
D8
DB8
DB8
Pin 8
D7
DB7
LOW
*D11...D0/8 are the ADC data output pins.
DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.
TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity
1.0
V
DD
= 5V
f
CLK
= 4MHz
0.5
INL ERROR (LSBs)
U W
UO
U
U
S
HBEN (Pin 19):
High Byte Enable Input. This pin is used to
multiplex the internal 12-bit conversion result into the
lower bit outputs (D7 to D0/8). See table below. HBEN also
disables conversion starts when HIGH.
RD (Pin 20):
Read Input. This active low signal starts a
conversion when CS and HBEN are low. RD also enables
the output drivers when CS is low.
CS (Pin 21):
The Chip Select Input must be low for the ADC
to recognize RD and HBEN inputs.
BUSY (Pin 22):
The BUSY Output is low when a conver-
sion is in progress.
NC (Pin 23):
Not Connected Internally. The LTC1272 does
not require negative supply. This pin can accommodate
the –15V required by the AD7572 without problems.
V
DD
(Pin 24):
Positive Supply, 5V.
Pin 9
D6
DB6
LOW
Pin 10
D5
DB5
LOW
Pin 11
D4
DB4
LOW
Pin 13
D3/11
DB3
DB11
Pin 14
D2/10
DB2
DB10
Pin 15
D1/9
DB1
DB9
Pin 16
D0/8
DB0
DB8
0
– 0.5
–1.0
0
512
1024
1536
2048
CODE
LTC1272 • TPC01
2560
3072
3584
4096
1272fb
5
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