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Data Sheet

A m p l i fy t h e H u m a n E x p e r i e n c e

CDK2307

Dual, 20/40/65/80MSPS, 12/13-bit

Analog-to-Digital Converters

CDK2307

Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters

FEATURES

n

General Description

The CDK2307 is a high performance, low power dual Analog-to-Digital Con-

verter (ADC). The ADC employs internal reference circuitry, a CMOS control

interface and CMOS output data, and is based on a proprietary structure.

Digital error correction is employed to ensure no missing codes in the com-

plete full scale range.

Several idle modes with fast startup times exist. Each channel can be inde-

pendently powered down and the entire chip can either be put in Standby

Mode or Power Down mode. The different modes are optimized to allow the

user to select the mode resulting in the smallest possible energy consumption

during idle mode and startup.

The CDK2307 has a highly linear THA optimized for frequencies up to 70MHz.

The differential clock interface is optimized for low jitter clock sources and

supports LVDS, LVPECL, sine wave and CMOS clock inputs.

13-bit resolution

20/40/65/80MSPS maximum sampling rate

Ultra-low power dissipation: 30/55/85/102mW

SNR 72dB at 80MSPS and 8MHz F

IN

Internal reference circuitry

1.8V core supply voltage

1.7V – 3.6V I/O supply voltage

Parallel CMOS output

64-pin QFN package

(TQFP-64 package option also available)

Dual channel

Pin compatible with CDK2308

n

APPLICATIONS

n

Handheld Communication, PMR, SDR

Medical Imaging

Portable Test Equipment

Digital Oscilloscopes

Baseband / IF Communication

Video Digitizing

CCD Digitizing

Functional Block Diagram

CLKN

CLK_EXT

CLKP

Ordering Information

Part Number

CDK2307AILP64

CDK2307BILP64

CDK2307CILP64

CDK2307DILP64

CDK2307AITQ64

CDK2307BITQ64

CDK2307CITQ64

CDK2307DITQ64

Speed

20MSPS

40MSPS

65MSPS

80MSPS

20MSPS

40MSPS

65MSPS

80MSPS

Package

QFN-64

TQFP-64

Pb-Free

Yes

RoHS Compliant

Yes

Operating Temperature Range

-40°C to +85°C

Packaging Method

Tray

Rev 2B

Moisture sensitivity level for all parts is MSL-2A.

www.cadeka.com

Data Sheet

Pin Configuration

QFN-64, TQFP-64

CDK2307

Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

1

2

3

4

5

6

7

8

9

10

11

12

DVSSCLK

DVDDCLK

CLKP

CLKN

49

48

47

46

45

44

QFN-64, TQFP-64

CDK2307

43

42

41

40

39

38

37

36

35

34

33

CLK_EXT

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

Pin Assignments

Pin No.

1, 18, 23

2

3, 9, 12

4, 5, 8

6, 7

10, 11

13

14

15

16

17, 64

19

20

21

22

24, 41, 58

25, 40, 57

26

27

28

29

Pin Name

DVDD

CM_EXT

AVDD

AVSS

IP0, IN0

IP1, IN1

DVSSCLK

DVDDCLK

CLKP

CLKN

DVSS

CLK_EXT_EN

DFRMT

PD_N

OE_N_1

OVDD

OVSS

D1_0

D1_1

D1_2

D1_3

Description

Digital and I/O-ring pre driver supply voltage, 1.8V

Common Mode voltage output

Analog supply voltage, 1.8V

Analog ground

Analog input Channel 0 (non-inverting, inverting)

Analog input Channel 1 (non-inverting, inverting)

Clock circuitry ground

Clock circuitry supply voltage, 1.8V

Clock input, non-inverting (Format: LVDS, PECL, CMOS/TTL, Sine Wave)

Clock input, inverting. For CMOS input on CLKP, connect CLKN to ground

Digital circuitry ground

CLK_EXT signal enabled when low (zero). Tristate when high.

Data format selection. 0: Offset Binary, 1: Two's Complement

Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up,

always apply Power Down mode before using Active Mode to reset chip.

Output Enable Channel 0. Tristate when high.

I/O ring post-driver supply voltage. Voltage range 1.7V to 3.6V.

Ground for I/O ring

Output Data Channel 1 (LSB, 13-bit output or 1V

pp

full scale range )

Output Data Channel 1 (LSB, 12-bit output 2V

pp

full scale range)

Output Data Channel 1

CLK_EXT_EN

Rev 2B

www.cadeka.com

2

Data Sheet

Pin Assignments

(Continued)

Pin No.

30

31

32

33

34

35

36

37

38

39

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

59

60, 61

Pin Name

D1_4

D1_5

D1_6

D1_7

D1_8

D1_9

D1_10

D1_11

D1_12

ORNG_1

CLK_EXT

D0_0

D0_1

D0_2

D0_3

D0_4

D0_5

D0_6

D0_7

D0_8

D0_9

D0_10

D0_11

D0_12

ORNG_0

OE_N_0

CM_EXTBC_1,

CM_EXTBC_0

SLP_N_1,

SLP_N_0

Description

Output Data Channel 1

Output Data Channel 1 (MSB for 1V

pp

full scale range, see Reference Voltages section)

Output Data Channel 1 (MSB for 2V

pp

full scale range)

Out of Range flag Channel 1. High when input signal is out of range

Output clock signal for data synchronization. CMOS levels.

Output Data Channel 0 (LSB, 13 bit output or 1Vpp full scale range)

Output Data Channel 0 (LSB, 12 bit output 2Vpp full scale range)

Output Data Channel 0

Output Data Channel 0 (MSB for 1V

pp

full scale range, see Reference Voltages section)

Output Data Channel 0 (MSB for 2V

pp

full scale range)

Out of Range flag Channel 0. High when input signal is out of range.

Output Enable Channel 0. Tristate when low.

Bias control bits for the buffer driving pin CM_EXT

00: Off

01: 50uA

10: 500uA

11: 1mA

Sleep Mode

00: Sleep Mode

10: Channel 1 active

01: Channel 0 active

11: Both channels active

CDK2307

Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters

62, 63

Rev 2B

www.cadeka.com

3

Data Sheet

Absolute Maximum Ratings

The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device

should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device

function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the

operating conditions noted on the tables and plots.

Parameter

AVDD, AVSS

DVDD, DVSS

AVSS, DVSSCLK, DVSS, OVSS

OVDD, OVSS

CKP, CKN, DVSSCLK

Analog inputs and outpts (IPx, INx, AVSS)

Digital inputs

Digital outputs

Min

-0.3

Max

+2.3

+0.3

+3.9

+2.3

+3.9

Unit

V

CDK2307

Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters

Reliability Information

Parameter

Junction Temperature

Storage Temperature Range

Lead Temperature (Soldering, 10s)

Min

-40

-60

J-STD-020

Typ

Max

85

+150

Unit

°C

ESD Protection

Product

Human Body Model (HBM)

QFN-64

2kV

TQFP-64

2kV

Recommended Operating Conditions

Parameter

Operating Temperature Range

Min

-40

Typ

Max

+85

Unit

°C

Rev 2B

www.cadeka.com

4

Data Sheet

Electrical Characteristics

(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle,

-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)

Symbol

DC Accuracy

No Missing Codes

Offset Error

Gain Error

Gain Matching

DNL

INL

V

CMO

Differential Non-Linearity

Integral Non-Linearity

Common Mode Voltage Output

Input Common Mode

Full Scale Range, Normal

V

FSR

Full Scale Range, Option

Input Capacitance

Bandwidth

Analog input common mode voltage

Differential input voltage range,

Differential input voltage range, 1V

(see section Reference Voltages)

Differential input capacitance

Input bandwidth, full power

Supply voltage to all 1.8V domain pins.

See Pin Configuration and Description

Output driver supply voltage (OVDD).

Must be higher than or equal to Core Supply

Voltage (VOVDD

≥

VDVDD)

500

1.7

1.8

2.5

2.0

3.6

V

CM

-0.1

2.0

1.0

2.0

Midscale offset

Full scale range deviation from typical

Gain matching between channels. ±3 sigma

value at worst case conditions.

12-bit level

-6

±0.5

±0.2

±0.6

VAVDD/2

V

CM

+0.2

Guaranteed

1

6

LSB

%FS

LSB

V

Vpp

pF

MHz

V

Parameter

Conditions

Min

Typ

Max

Units

CDK2307

Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters

Analog Input

V

CMI

Power Supply

AVDD, DVDD

OVDD

Core Supply Voltage

I/O Supply Voltage

Rev 2B

www.cadeka.com

5

CDK2307CITQ64

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