THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
MV6001
ADVANCE INFORMATION
DS3138-2.1
MV6001
HDLC/DMA CONTROLLER
The MV6001 is a combined HDLC transceiver and DMA
controller capable of providing serial communications at rates
up to 128K bits/second, and handling direct memory access
clock rates up to 8MHz.
GND
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
GND
TST
A
8
/D
0
A
9
/D
1
A
10
/D
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
V
CC
MRD
MWR
MR
BRQ
BAK
CS
DMACK
RD
WR
MODE
TX
OP
T
CK
R
CK
RX
IP
AEN
ASB
R
INT
T
INT
T
OP2
FEATURES
s
s
s
s
s
s
s
Data Rates up to 128K Bits/s
DMA Rate up to 8MHz
Low Power CMOS
Simple Interfacing to Popular 8-Bit Processors
Frame Length up to 2K Bytes
Low Host-Processor Overhead
Conforms to ECMA40 and Related Standards
(CCITT X25, X75, 1.440, ISO3309, ANSI X3.66,
FED-STD 1003, FIPS71)
MV6001
31
30
29
28
27
26
25
24
23
22
21
APPLICATIONS
s
ISDN Terminals
s
LANs
s
X25 p.s.s. Networks
A
11
/D
3
A
12
/D
4
A
13
/D
5
A
14
/D
6
A
15
/D
7
ORDERING INFORMATION
MV6001 B0 DP
(Commercial Plastic DIP)
MV6001 B0 DG
(Commercial Ceramic DIP)
GND
DP40
DG40
Figure 1: Pin connections - top view
OP T
OP2
T
INT
TCK
R
INT
RX
IP
RCK
TX
DMA
RX
REGISTERS
ADDRESS/
DATA
BUS
ADDRESS
BUS
BRQ
ASB
MRD
CS
MODE
MWR
AEN
BAK
TFL
TA
S
C
RFL
RMFL
RA
A8/D0, A15/D7
A0, A7
WR
RD
MR
TST
Figure 2: Block diagram
1
MV6001
PIN DESCRIPTION
Pin No.
1,10,20
2-9
11
12-19
21
22
Name
GND
A
0
- A
7
TST
A
8
/D
0
- A
15
/D
7
TOP2
T
INT
I/O
I
I/O
O
O
I/O
Function
0V supply.
All 3 pins must be connected.
Address Bus.
Output for memory A
0
- A
7
addressing. Input for register
addresses A
0
- A
3
.
Test Enable.
Tie to GND for normal operation.
Data Bus/High Order Address.
Multiplexed data and address bus.
Transmitter Out.
Alternative output to TX
OP
. This output is not affected by
loop back (see Operating Notes - LOOPBACK).
Transmitter Interrupt.
An interrupt is generated whenever transmission
of a frame is ended, either following the last FCS byte of a complete frame of when
an abort sequence is transmitted. The interrupt is reset by the control
register.
Receiver Interrupt.
An interrupt is generated whenever a frame is received.
The interrupt is reset by the counter register.
Address Strobe.
Strobes the Address High byte from the
Data/Address Bus into an external latch.
Address Enable.
Enables the external address latch.
Receiver Input.
Serial HDLC data input, clocked in by RCK.
Receiver Data Clock.
Provides clock to the receiver section, frequency
should be at the required data rate, this need not necessarily the the same as the
transmit data rate.
Transmitter Data Clock.
This input provides a clock signal for the
transmitter section and should be set to the desired transmit data rate.
Transmitter output.
Main transmitter output for serial data.
Bus Control Mode Select.
Controls the polarity of BAK and BRQ.
MODE = V
CC
gives active LOW, MODE = GND gives active HIGH.
Write Register.
Loads data from data bus into register addressed by A
0
- A
3
.
Read Register.
Reads addressed register onto data bus
DMA Clock.
This input provides clock to the DMA section. The DMA clock rate
should be at least ten times the sum of the transmit and receive data rates.
Chip Select.
Enables
RD
and
WR
inputs.
Bus Acknowledge.
Input from processor relinquishing control of bus. See
pin 30, Bus Mode Select.
Bus Request.
Output to processor requesting the bus for a DMA cycle. See pin
30, Bus Mode Select.
Master Reset.
Resets everything.
Memory Write.
This is a three-state output to write data into memory during
DMA cycles.
Memory Read.
3-state output to read data from memory during DMA cycles.
±5V ±10%
supply.
23
24
25
26
27
R
INT
ASB
AEN
RX
IP
RCK
O
O
O
I
I
28
29
30
31
32
33
34
35
36
37
38
39
40
TCK
TX
OP
MODE
WR
RD
DMACK
CS
BAK
BRQ
MR
MWR
MRD
V
CC
I
O
I
I
I
I
I
I
O
I
O
O
2
MV6001
USER FIELDS
≤2047
BYTES
01111110
FLAG
START
ADDRESS
1 OR N* BYTES
CONTROL
1 OR 2 BYTES
DATA
FRAME CHECK SEQUENCE
2 BYTES
01111110
FLAG
FINISH
MV6001 GENERATED
*N is any integer
Figure 3
Fig.3 shows the construction of an HDLC frame. The start
and finish of the frame are determined by FLAGS (the binary
pattern 01111110). To prevent spurious recognition of flags in
the user fields, the transmitter automatically inserts a ‘0’ after
five successive ‘1 ‘s. The inserted ‘0’s are removed by the
receiver, and hence are not seen by the user. Each HDLC
frame contains a 2 byte frame check sequence produced by a
cyclic redundancy generator in the transmitter. This sequence
is checked by the receiver to validate the frame.
There are two other sequences which have specific
meanings - IDLE and ABORT. The IDLE state is the
transmission of at least 15 continuous ‘1’s without inserted
zeros. ABORT is 7 to 14 consecutive ‘1’s without inserted
zeros sandwiched between two zeros.
at any time to start transmission. Once a transmission has
been started, the only way it can by stopped is to set the abort
bit (D1). The transmitter will then transmit the abort sequence
followed by flags. Transmitter reset (D2) resets the transmitter
interrupt TINT, clears the TA and TFL registers and bits D0
and D1 of the status register. Transmitter reset is disabled
during a transmission.
INTERRUPT
A transmitter interrupt (T
INT
) is generated whenever a
transmission ceases, the status register can then be read to
check if the frame was aborted or not. The interrupt is reset by
writing a transmitter reset to the control register. NB. The
status register must be read before a transmitter reset as this
will alter the contents of the status register.
STATUS
The transmitter has two status bits - transmitting data (Do)
and abort (D1) The transmitting data bit should always be low
after T
INT
signifying that transmission is ended. The abort bit
will be high whenever a frame is aborted either by an abort
instruction to the control register, or internally due to an under-
run .
RECEPTION
The receiver accepts serlal data, removes inserted zeros
and checks the frame check sequence. For each byte of data
received, the receiver section generates a DMA request to
transfer the data to memory. If the DMA controller fails to make
the transfer before the next request from the receiver, then the
receiver will drop out and give a receiver. interrupt with the
code in the status register for overrun. If the number of bytes
received reaches the number in the receive maximum frame
length registerthe receiverwilldropoutand give an interrupt with
the code in the status register for frame too long.
INITIALISATION
The RA register (2 bytes) is loaded with the address where
the first received byte of data is to be stored. The RMFL
register (11 bits) is loaded with the maximum number of bytes
in the user fields plus 3 bytes ( +2 bytes for the FCS, +1 byte
because an interrupt will occur when the frame length is equal
to the length set by the number in the register) .
FUNCTIONAL DESCRIPTION
The MV6001 consists of four main sections; transmitter,
receiver, DMA unit and register bank. Each of the transminer~
receiver and DMA unit have their own clocks running at the
required data rates. There are no restrictions on the relative
timing between transmit and receive clocks, the DMA clock
rate should be greater than ten times the sum of the transmit
and receive clock rates.
TRANSMISSION
In its steady state the transmitter produces a continuous
stream of FLAGS until the control register is loaded with a
transmit instruction. The transmitter then, at intervals, requests
the DMA unit to fetch a byte of data. This is then transferred
from the system memory via the data bus to the transmitter. (If
the DMA unit should fail to fetch a byte of data by the time the
next request arrives then an under-run will occur and the
transmitter will transmit an ABORT sequence). Data is
converted into a serial stream with inserted zeros after five
ones, and the 16-bit frame check sequence is appended at the
end of each frame. As soon as the last bit of the FCS has been
clocked out, the TINT OUtPUt goes low to inform the
processor that transmission has ended.
INITIALISATION
To start transmission, two items of information are required
- the start address for the data to be transmitted, and the length
of the user fields are loaded into the TA and TFL registers
respectively, after which the transmit enable bit (D0) can be set
3
MV6001
CONTROL
The receiver has two control bits in the control register,
receive enable (D3) and receive reset (D4). Once the RA and
RMFL registers have been loaded, the receive enable bit can
be set at any time to allow the receiver to receive a frame.
Once set, the receive enable bit cannot be overwritten and
receive reset is disabled until a frame has been received.
Receiver reset will reset the
R
lNT
interrupt bit, registers
RFL, RMFL, RA and bits D2 - D7 of the status register.
INTERRUPT
A receive interrupt (R
INT
) is generated whenever a frame is
received. The status register can then be read to check the
status of the received frame. The interrupt is reset by writing a
receiver reset to the control register. Since the reset will clear
the receiver bits in the status register, the register must be read
before writing the reset to the control register.
STATUS
The receiver uses bits D2 - D7 of the status register (see
Figs. 5 and 6). A valid frame is indicated by both ‘overrun’ (D6)
and ‘frame too long’ (D7) bits being high. Following R
INT
the
‘free to receive’ bit (D2) should be low, indicating that a frame
has been received. The abort, overrun and long frame bits will
be set according to the state of the frame received. The flag
(D4) and idle (D3) bits monitor the incoming signal
continuously even when the receiver is disabled.
2 FCS bytes in the count. The reqister should be read before a
receiver reset.
LOOPBACK
Bit D7 of the control register, the loopback bit is provided
for testing purposes. When the bit is set high an internal
connection is made between the transmitter output and
receiver input. The main transmitter output (TX
OP
) transmits
IDLE (transmitted data is always available on T
OP2
). The
receiver is clocked from TCK. The loopback bit will respond to
every write to the control register.
DIRECT MEMORY ACCESS (FIG.11)
All data transfers to or from memory are carried out by the
DMA controller. Each time it receives a request from the
transmitter or receiver it will carry out one DMA cycle, i.e. only
one byte is transferred at a time. Clashes between transmitter
and receiver are resolved in favour of the receiver, otherwise
operation is on a first come, first served basis.
REGISTERS
Fig.7 shows the addresses for the various instruction and
status registers. All registers are readable from and writable to
except for S, C and RFL. The S and C registers have the same
address, which one is accessed is determined by whether a
read (status) or write (control) operation is carried out.
Transmitter registers should not be written to when
transmitting (except to ABORT a frame), likewise receiver
registers should not be written to when receiving. The TA and
RA registers update continuously during transmission and
reception respectively, giving the next address to be read from
or written to.
FRAME LENGTH REGISTER
Having received a frame and read the status reqister, the
received frame length can be read from the RFL register. The
frame length is given as an eleven bit number and includes the
D
7
LOOPBACK
ENABLE
D
6
DON'T
CARE
D
5
DON'T
CARE
D
4
RECEIVE
RESET
D
3
RECEIVE
ENABLE
D
2
TRANSMIT
RESET
D
1
TRANSMIT
ABORT
D
0
TRANSMIT
ENABLE
Figure 4: Control register
D
7
RECEIVED
FRAME
TOO LONG
D
6
RECEIVED
OVERRUN
FRAME
D
5
RECEIVED
ABORT
D
4
RECEIVING
FLAGS
D
3
RECEIVING
IDLE
D
2
FREE TO
RECEIVE
D
1
TRANS-
MISSION
ABORTED
D
0
TRANS-
MITTING
DATA
RECEIVE BITS
TRANSMIT BITS
Figure 5: Status register
4
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