DATASHEET
X9119
1024 Tap, Low Power, 2-Wire Interface, Digitally Controlled (XDCP™)
Potentiometer
The
X9119
integrates a single digitally controlled
potentiometer (XDCP™) on a monolithic CMOS integrated
circuit.
The digital controlled potentiometer is implemented using
1023 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-wire bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and four nonvolatile data registers that can be
directly written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor array
through the switches. Power-up recalls the contents of the
default data register (DR0) to the WCR.
The XDCP™ can be used as a 3-terminal potentiometer or as a
2-terminal variable resistor in a wide variety of applications
including control, parameter adjustments and signal
processing.
FN8162
Rev 5.00
July 5, 2016
Features
• 1024 resistor taps – 10-bit resolution
• 2-Wire serial interface for write, read, and
transfer operations of the potentiometer
• Wiper resistance, 40Ω typical at V
CC
= 5V
• Four nonvolatile data registers
• Nonvolatile storage of multiple wiper positions
• Power-on recall, loads saved wiper position on power-up.
• Standby current <3µA maximum
• V
CC
: 2.7V to 5.5V operation
• 100kΩ end-to-end resistance
• 100 yr. data retention
• Endurance: 100,000 data changes per bit per register
• 14 Ld TSSOP
• Low power CMOS
• Single supply version of the X9118
• Pb-free available (RoHS compliant)
V
CC
R
H
2-WIRE
BUS
INTERFACE
ADDRESS
DATA
STATUS
BUS
INTERFACE
AND
CONTROL
WRITE
READ
TRANSFER
POWER-ON RECALL
WIPER COUNTER
REGISTER (WCR)
DATA REGISTERS
(DR0-DR3)
WIPER
100kΩ
1024-TAPS
POT
CONTROL
V
SS
NC
NC
R
W
R
L
FIGURE 1. FUNCTIONAL DIAGRAM
FN8162 Rev 5.00
July 5, 2016
Page 1 of 18
X9119
Applications
Circuit Level
• Vary the gain of a voltage amplifier
• Provide programmable DC reference voltages for comparators
and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in filter
circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the DC biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits
System Level
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in communication
systems
• Set and regulate the DC biasing point in an RF power amplifier
in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent
systems
Ordering Information
PART NUMBER
(Notes
2, 3)
X9119TV14IZ
X9119TV14Z
X9119TV14Z-2.7
X9119TV14IZ-2.7 (Note
1)
NOTES:
1. Add “T1” suffix for 2.5k unit tape and reel option.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for
X9119.
For more information on MSL, please see tech brief
TB363.
PART MARKING
X9119 TVZI
X9119 TVZ
X9119 TVZF
X9119 TVZG
2.7 to 5.5
V
CC
LIMITS
(V)
5 ±10%
POTENTIOMETER
ORGANIZATION
(kΩ)
100
TEMP
RANGE
(°C)
PACKAGE
RoHS COMPLIANT
PKG. DWG.#
M14.173
M14.173
M14.173
M14.173
-40 to +85 14 Ld TSSOP (4.4mm)
0 to +70
0 to +70
14 Ld TSSOP (4.4mm)
14 Ld TSSOP (4.4mm)
-40 to +85 14 Ld TSSOP (4.4mm)
V
CC
POWER ON
RECALL
SCL
SDA
A2
A1
A0
WP
DR0
INTERFACE
AND
CONTROL
CIRCUITRY
DATA
DR2
CONTROL
R
W
DR3
DR1
WIPER
COUNTER
REGISTER
(WCR)
100kΩ
1024-TAPS
R
L
R
H
V
SS
FIGURE 2. DETAILED FUNCTIONAL DIAGRAM
FN8162 Rev 5.00
July 5, 2016
Page 2 of 18
X9119
Pin Configuration
X9119
(14 LD TSSOP)
TOP VIEW
NC
A0
NC
A2
SCL
SDA
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
R
L
R
H
R
W
NC
A1
WP
DEVICE ADDRESS (A
2
–A
0
)
The Address inputs are used to set the least significant 3 bits of
the 8-bit slave address. A match in the slave address serial data
stream must be made with the Address input in order to initiate
communication with the X9119. A maximum of 8 devices may
occupy the 2-wire serial bus.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW, prevents nonvolatile writes to the Data
Registers.
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal connections on
a mechanical potentiometer.
Pin Assignments
PIN
NUMBER
1, 3, 10
2
4
5
6
7
8
9
11
12
13
14
PIN NAME
NC
A0
A2
SCL
SDA
V
SS
WP
A1
R
W
R
H
R
L
V
CC
No connect
Device address for 2-wire bus
Device address for 2-wire bus
Serial clock for 2-wire bus
Serial data input/output for 2-wire bus
System ground
Hardware write protect
Device address for 2-wire bus
Wiper terminal of the potentiometer
High terminal of the potentiometer
Low terminal of the potentiometer
System supply voltage
FUNCTION
R
W
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (V
CC
) AND SUPPLY
GROUND (V
SS
)
The V
CC
pin is the system supply voltage. The V
SS
pin is the
system ground.
Other Pins
NO CONNECT
No connect pins should be left open. These pins are used for
Intersil manufacturing and testing purposes.
Principals of Operation
The X9119 is an integrated microcircuit incorporating a resistor
array and its associated registers and counters and the serial
interface logic providing direct communication between the host
and the digitally controlled potentiometer. This section provides
detail description of the following:
• Resistor Array Description
• Serial Interface Description
• Instruction and Register Description
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for a
2-wire slave device and is used to transfer data into and out of
the device. It receives device address, opcode, wiper register
address and data sent from a 2-wire master at the rising edge of
the serial clock SCL, and it shifts out data after each falling edge
of the serial clock SCL.
It is an open-drain output and may be wire-ORed with any
number of open-drain or open collector outputs. An open-drain
output requires the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical values on the
bus pull-up resistors graph.
Resistor Array Description
The X9119 is comprised of a resistor array. The array contains, in
effect, 1023 discrete resistive segments that are connected in
series (Figure
3 on page 4).
The physical ends of each array are
equivalent to the fixed terminals of a mechanical potentiometer
(R
H
and R
L
inputs).
At both ends of each array and between each resistor segment is
a CMOS switch connected to the wiper (R
W
) output. Within each
individual array only one switch may be turned on at a time.
These switches are controlled by the Wiper Counter Register
(WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to select,
and enable, one of 1024 switches.
SERIAL CLOCK (SCL)
This input is used by a 2-wire master to supply a 2-wire serial
clock to the X9119.
FN8162 Rev 5.00
July 5, 2016
Page 3 of 18
X9119
The WCR may be written directly. The data registers and the WCR
can be read and written by the host system.
ACKNOWLEDGE
Acknowledge is a software convention used to provide a positive
handshake between the master and slave devices on the bus to
indicate the successful receipt of data. The transmitting device,
either the master or the slave, will release the SDA bus after
transmitting eight bits. The master generates a ninth clock cycle
and during this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits of data.
The X9119 will respond with an acknowledge after recognition of
a start condition and its slave address and once again after
successful receipt of the command byte. If the command is
followed by a data byte the X9119 will respond with a final
acknowledge (see
Figure 4).
Serial Interface Description
SERIAL INTERFACE
The X9119 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is a master and the device being
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the X9119 will be considered a slave
device in all applications.
CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions (Figure
6 on page 8).
ACKNOWLEDGE POLLING
The disabling of the inputs, during the internal nonvolatile write
operation, can be used to take advantage of the typical 5ms
EEPROM write cycle time. Once the stop condition is issued to
indicate the end of the nonvolatile write command the X9119
initiates the internal write cycle. ACK polling, Flow 1 (see
Figure 5 on page 5),
can be initiated immediately. This involves
issuing the start condition followed by the device slave address. If
the X9119 is still busy with the write operation, no ACK will be
returned. If the X9119 has completed the write operation, an
ACK will be returned and the master can then proceed with the
next operation.
START CONDITION
All commands to the X9119 are preceded by the start condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH. The
X9119 continuously monitors the SDA and SCL lines for the start
condition and will not respond to any command until this
condition is met (Figure
6).
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is HIGH (see
Figure 6).
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
REGISTER 1
(DR1)
SERIAL
BUS
INPUT
C
O
U
N
T
E
R
D
E
C
O
D
E
R
RH
10
10
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR)
REGISTER 2
(DR2)
REGISTER 3
(DR3)
IF WCR = 000[HEX] THEN R
W
= R
L
IF WCR = 3FF[HEX] THEN R
W
= R
H
RL
R
W
FIGURE 3. DETAILED POTENTIOMETER BLOCK DIAGRAM SERIAL INTERFACE DESCRIPTION
FN8162 Rev 5.00
July 5, 2016
Page 4 of 18
X9119
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ST AR T
ACKNO WLEDGE
FIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVER
NONVOLATILE WRITE
COMMAND COMPLETED
ENTER ACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS
ISSUE STOP
ACK
RETURNED?
YES
NO
FURTHER
OPERATION?
NO
YES
ISSUE
INSTRUCTION
ISSUE STOP
PROCEED
PROCEED
FIGURE 5. FLOW 1. ACK POLLING SEQUENCE
FN8162 Rev 5.00
July 5, 2016
Page 5 of 18
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