DATASHEET
X9221A
64 Taps, 2-Wire Serial Bus Dual Digitally Controlled Potentiometer (XDCP™)
FEATURES
• Two XDCPs in one package
• 2-wire serial interface
• Register oriented format, 8 registers total
—Directly write wiper position
—Read wiper position
—Store as many as four positions per pot
• Instruction format
—Quick transfer of register contents to resistor
array
• Direct write cell
—Endurance–100,000 writes per bit per register
• Resistor array values
—2k, 10k, 50k
• Resolution: 64 taps each pot
• 20 Ld plastic DIP and 20 Ld SOIC packages
• Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X9221A integrates two digitally controlled potenti-
ometers (XDCP) on a monolithic CMOS integrated
microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 2 non-
volatile Data Registers (DR0:DR1) that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array through the switches. Power up recalls the con-
tents of DR0 to the WCR.
The XDCP can be used as a three-terminal potentiom-
eter or as a two-terminal variable resistor in a wide
variety of applications including control, parameter
adjustments, and signal processing.
BLOCK DIAGRAM
Pot 0
V
CC
V
SS
R0 R1
Wiper
Counter
Register
(WCR)
V
H0
/R
H0
FN8163
Rev 2.00
August 30, 2006
R2 R3
SCL
SDA
A0
A1
A2
A3
V
L0
/R
L0
V
W0
/R
W0
Interface
and
Control
Circuitry
Data
8
R0 R1
V
H1
/R
H1
Wiper
Counter
Register
(WCR)
Register
Array
Pot 1
R2 R3
V
L1
/R
L1
V
W1
/R
W1
FN8163 Rev 2.00
August 30, 2006
Page 1 of 15
X9221A
Ordering Information
PART NUMBER
X9221AYS
X9221AYSZ (Note)
X9221AYSI*
X9221AYSIZ* (Note)
X9221AWS*
X9221AWSZ* (Note)
X9221AWSI*
X9221AWSIZ* (Note)
X9221AUP
X9221AUPZ (Note)
X9221AUPI
X9221AUPIZ (Note)
X9221AUSI*
X9221AUSIZ* (Note)
PART MARKING
X9221AYS
X9221AYS Z
X9221AYSI
X9221AYSI Z
X9221AWS
X9221AWS Z
X9221AWSI
X9221AWSI Z
X9221AUP
X9221AUPZ
X9221AUPI
X9221AUPIZ
X9221AUSI
X9221AUSI Z
50
10
V
CC
LIMITS
(V)
5 ±10%
R
TOTAL
(k)
2
TEMP
RANGE (°C)
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
20 Ld SOIC (300MIL)
20 Ld SOIC (300MIL) (Pb-Free)
20 Ld SOIC (300MIL)
20 Ld SOIC (300MIL) (Pb-Free)
20 Ld SOIC (300MIL)
20 Ld SOIC (300MIL) (Pb-Free)
20 Ld SOIC (300MIL)
20 Ld SOIC (300MIL) (Pb-Free)
20 Ld PDIP
20 Ld PDIP (Pb-Free)
20 Ld PDIP
20 Ld PDIP (Pb-Free)
20 Ld SOIC (300MIL)
20 Ld SOIC (300MIL) (Pb-Free)
PKG.
DWG. #
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
MDP0031
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9221A.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open col-
lector outputs. An open drain output requires the use of
a pull-up resistor. For selecting typical values, refer to
the guidelines for calculating typical values on the bus
pull-up resistors graph.
Address
The Address inputs are used to set the least significant 4
bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with the
X9221A
Potentiometer Pins
V
H
/R
H
(V
H0
/R
H0
-V
H1
/R
H1
), V
L
/R
L
(V
L0
/R
L0
-V
L1
/R
L1
)
The V
H
/R
H
and V
L
/R
L
inputs are equivalent to the termi-
nal connections on either end of a mechanical potenti-
ometer.
V
W
/R
W
(V
W0
/R
W0
-V
W1
/R
W1
)
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
PIN CONFIGURATION
DIP/SOIC
V
W0
/R
W0
V
L0
/R
L0
V
H0
/R
L0
A0
A2
V
W1
/R
W1
V
L1
/R
L1
V
H1
/R
H1
SDA
V
SS
1
2
3
4
5
6
7
8
9
10
X9221A
20
19
18
17
16
15
14
13
12
11
V
CC
RES
RES
RES
A1
A3
SCL
RES
RES
RES
FN8163 Rev 2.00
August 30, 2006
Page 2 of 15
X9221A
PIN NAMES
Symbol
SCL
SDA
A0–A3
V
H0
/R
H0
-V
H1
/R
H1
,
V
L0
/R
H0
-V
L1
/R
L0
V
W0
/R
W0
-V
W1
/R
W1
RES
Acknowledge
Description
Serial Clock
Serial Data
Address
Potentiometers
(terminal equivalent)
Potentiometers
(wiper equivalent)
Reserved (Do not connect)
Acknowledge is a software convention used to provide a
positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits
of data. See Figure 7.
The X9221A will respond with an acknowledge after rec-
ognition of a start condition and its slave address and
once again after successful receipt of the command
byte. If the command is followed by a data byte the
X9221A will respond with a final acknowledge.
Array Description
The X9221A is comprised of two resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical potenti-
ometer (V
H
/R
H
and V
L
/R
L
inputs).
At both ends of each array and between each resistor
segment is a FET switch connected to the wiper
(V
W
/R
W
) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six least significant bits of the WCR are decoded to
select, and enable, one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type identi-
fier (refer to Figure 1 below). For the X9221A this is fixed
as 0101[B].
Figure 1. Slave Address
Device Type
Identifier
0
1
0
1
A3
A2
A1
A0
PRINCIPLES OF OPERATION
The X9221A is a highly integrated microcircuit incorpo-
rating two resistor arrays, their associated registers and
counters and the serial interface logic providing direct
communication between the host and the XDCP potenti-
ometers.
Serial Interface
The X9221A supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers and provide the
clock for both transmit and receive operations. There-
fore, the X9221A will be considered a slave device in all
applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods (t
LOW
). SDA state changes during SCL
HIGH are reserved for indicating start and stop condi-
tions.
Start Condition
All commands to the X9221A are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t
HIGH
). The X9221A continuously
monitors the SDA and SCL lines for the start condition,
and will not respond to any command until this condition
is met.
Stop Condition
All communications must be terminated by a stop condi-
tion, which is a LOW to HIGH transition of SDA while
SCL is HIGH.
Device Address
FN8163 Rev 2.00
August 30, 2006
Page 3 of 15
X9221A
The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A0-A3 inputs. The X9221A compares the
serial data stream with the address input state; a suc-
cessful compare of all four address bits is required for
the X9221A to respond with an acknowledge.
Acknowledge Polling
The disabling of the inputs, during the internal nonvola-
tile write operation, can be used to take advantage of the
typical 5ms EEPROM write cycle time. Once the stop
condition is issued to indicate the end of the nonvolatile
write command the X9221A initiates the internal write
cycle. ACK polling can be initiated immediately. This
involves issuing the start condition followed by the
device slave address. If the X9221A is still busy with the
write operation no ACK will be returned. If the X9221A
has completed the write operation an ACK will be
returned and the master can then proceed with the next
operation.
Flow 1. ACK Polling Sequence
Nonvolatile Write
Command Completed
Enter ACK Polling
Instruction Structure
The next byte sent to the X9221A contains the instruc-
tion and register pointer information. The four most sig-
nificant bits are the instruction. The next four bits point to
one of two pots and when applicable they point to one of
four associated registers. The format is shown below in
Figure 2.
Figure 2. Instruction Byte Format
t
Potentiometer
Select
I3
I2
I1
I0
0
P0
R1
R0
Instructions
Register
Select
The four high order bits define the instruction. The sixth
bit (P0) selects which one of the two potentiometers is to
be affected by the instruction. The last two bits (R1 and
R0) select one of the four registers that is to be acted
upon when a register oriented instruction is issued.
Four of the nine instructions end with the transmission of
the instruction byte. The basic sequence is illustrated in
Figure 3. These two-byte instructions exchange data
between the WCR and one of the data registers. A trans-
fer from a data register to a WCR is essentially a write to
a static RAM. The response of the wiper to this action
will be delayed t
STPWV
. A transfer from WCR’s current
wiper position to a data register is a write to nonvolatile
memory and takes a minimum of t
WR
to complete. The
transfer can occur between either potentiometer and
their associated registers or it may occur between both
of the potentiometers and one of their associated regis-
ters.
Four instructions require a three-byte sequence to com-
plete. These instructions transfer data between the host
and the X9221A; either between the host and one of the
data registers or directly between the host and the WCR.
These instructions are: Read WCR, read the current
wiper position of the selected pot; Write WCR, change
current wiper position of the selected pot; Read Data
Register, read the contents of the selected nonvolatile
register; Write Data Register, write a new value to the
selected data register. The sequence of operations is
shown in Figure 4.
The Increment/Decrement command is different from
the other commands. Once the command is issued and
the X9221A has responded with an acknowledge, the
master can clock the selected wiper up and/or down in
one segment steps; thereby, providing a fine tuning
capability to the host. For each SCL clock pulse (t
HIGH
)
Issue
START
Issue Slave
Address
Issue STOP
ACK
Returned?
YES
NO
Further
Operation?
YES
Issue
Instruction
NO
Issue STOP
Proceed
Proceed
FN8163 Rev 2.00
August 30, 2006
Page 4 of 15
X9221A
while SDA is HIGH, the selected wiper will move one
resistor segment towards the V
H
/R
H
terminal. Similarly,
for each SCL clock pulse while SDA is LOW, the
selected wiper will move one resistor segment towards
Figure 3. Two-Byte Command Sequence
the V
L
/R
L
terminal. A detailed illustration of the
sequence and timing for this operation are shown in Fig-
ures 5 and 6 respectively.
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
0
P0
R1 R0
A
C
K
S
T
O
P
Figure 4. Three-Byte Command Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1 A3 A2 A1 A0 A
C
K
I3 I2
I1 I0
0
P0 R1 R0 A
C
K
0
0
D5 D4 D3 D2 D1 D0 A
C
K
S
T
O
P
Figure 5. Increment/Decrement Command Sequined
e
SCL
SDA
S
T
A
R
T
X
X
0
1
0
1
A3 A2 A1 A0
A
C
K
I3
I2
I1
I0
0
P0 R1 R0 A
C
K
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
S
T
O
P
FN8163 Rev 2.00
August 30, 2006
Page 5 of 15
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