Intel® Celeron® M Processor
on 65 nm Process
Datasheet
January 2007
Document Number: 312726-004
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
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TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
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use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Celeron® M processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
ΔIntel
processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different
processor families. See http://www.intel.com/products/processor_number for details.
Intel, Celeron, Pentium, MMX, and the Intel logo are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the United States
and other countries.
* Other brands and names are the property of their respective owners.
Copyright © 2006 – 2007, Intel Corporation. All rights reserved.
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Datasheet
Contents
1
Introduction
.............................................................................................................. 7
1.1
Terminology ....................................................................................................... 8
1.2
References ......................................................................................................... 9
Low Power Features
................................................................................................ 11
2.1
Clock Control and Low Power States .................................................................... 11
2.1.1 Core Low-Power States ........................................................................... 12
2.1.2 Package Low Power States ...................................................................... 13
2.2
FSB Low Power Enhancements ............................................................................ 15
2.3
Processor Power Status Indicator (PSI#) Signal..................................................... 16
Electrical Specifications
........................................................................................... 17
3.1
FSB (Front Side Bus) and GTLREF........................................................................ 17
3.2
Power and Ground Pins ...................................................................................... 17
3.3
Decoupling Guidelines ........................................................................................ 17
3.3.1 VCC Decoupling...................................................................................... 18
3.3.2 FSB AGTL+ Decoupling ........................................................................... 18
3.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking ........................................... 18
3.4
Voltage Identification and Power Sequencing ........................................................ 18
3.5
Catastrophic Thermal Protection .......................................................................... 22
3.6
Signal Terminations and Unused Pins ................................................................... 22
3.7
FSB Frequency Select Signals (BSEL[2:0])............................................................ 23
3.8
FSB Signal Groups............................................................................................. 23
3.9
CMOS Signals ................................................................................................... 25
3.10 Maximum Ratings.............................................................................................. 25
3.11 Processor DC Specifications ................................................................................ 25
Package Mechanical Specifications and Pin Information
.......................................... 31
4.1
Processor Component Keep-Out Zones ................................................................. 31
4.2
Package Loading Specifications ........................................................................... 31
4.3
Processor Mass Specifications ............................................................................. 31
4.4
Processor Pinout and Pin List .............................................................................. 36
4.5
Alphabetical Signals Reference ............................................................................ 55
Thermal Specifications and Design Considerations
.................................................. 63
5.1
Thermal Specifications ....................................................................................... 65
5.1.1 Thermal Diode ....................................................................................... 65
5.1.2 Thermal Diode Offset .............................................................................. 68
5.1.3 Intel® Thermal Monitor........................................................................... 68
5.1.4 Digital Thermal Sensor............................................................................ 70
5.1.5 Out of Specification Detection .................................................................. 70
5.1.6 PROCHOT# Signal Pin ............................................................................. 70
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3
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Datasheet
3
Figures
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Package-Level Low Power States ................................................................................11
Core Low Power States..............................................................................................12
Active V
CC
and I
CC
Loadline for the Celeron M Processor Standard Voltage .......................28
Active V
CC
and I
CC
Loadline for the Celeron M Processor Ultra Low Voltage .......................28
Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ................................................32
Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) ................................................33
Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) ................................................34
Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) ................................................35
Coordination of Core-Level Low Power States at the Package Level for the Celeron M
Processor ................................................................................................................11
Voltage Identification Definition ..................................................................................19
BSEL[2:0] Encoding for BCLK Frequency......................................................................23
FSB Pin Groups ........................................................................................................24
Processor DC Absolute Maximum Ratings.....................................................................25
Voltage and Current Specifications for the Celeron M Processor Standard Voltage..............26
Voltage and Current Specifications for the Celeron M Processor Ultra Low Voltage .............27
FSB Differential BCLK Specifications ............................................................................29
AGTL+ Signal Group DC Specifications ........................................................................29
CMOS Signal Group DC Specifications..........................................................................30
Open Drain Signal Group DC Specifications ..................................................................30
The Coordinates of the Processor Pins As Viewed from the Top of the Package .................36
Pin Listing by Pin Name .............................................................................................39
Pin Listing by Pin Number ..........................................................................................46
Signal Description.....................................................................................................55
Power Specifications for the Celeron M Processor Standard Voltage .................................64
Power Specifications for the Celeron M Processor Ultra Low Voltage.................................65
Thermal Diode Interface ............................................................................................66
Thermal Diode Parameters using Diode Model ..............................................................66
Thermal Diode Parameters using Transistor Mode .........................................................67
Thermal Diode n
trim
and Diode Correction Toffset..........................................................68
Tables
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Datasheet
Revision History
Revision
-001
Initial release
•
-002
•
Chapter 3, “Electrical Specifications”
— Added 440 and 450 processor specifications to
Table 6.
Chapter 5, “Thermal Specifications and Design Considerations”
— Added power specifications for the 440 and 450 processor
to
Table 16.
Corrected page numbering in
Chapter 5
Chapter 3, “Electrical Specifications”
— Added 443 ULV processor specifications to
Table 7.
Chapter 5, “Thermal Specifications and Design Considerations”
Added power specifications for the 443 ULV processor to
Table 17.
Description
Date
April 2006
September 2006
-003
•
•
September 2006
-004
•
•
January 2007
§
Datasheet
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