DATASHEET
X9250
Low Noise/Low Power/SPI Bus/256 Taps Quad Digitally Controlled
Potentiometers (XDCP™)
FEATURES
•
•
•
•
•
•
•
•
Four potentiometers in one package
256 resistor taps/pot - 0.4% resolution
SPI serial interface
Wiper resistance, 40 typical @ V
CC
= 5V
Four nonvolatile data registers for each pot
Nonvolatile storage of wiper position
Standby current < 5µA max (total package)
Power supplies
—V
CC
= 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
100k, 50k total pot resistance
High reliability
—Endurance – 100,000 data changes per bit per
register
—Register data retention - 100 years
24 Ld SOIC, 24 Ld TSSOP
Dual supply version of X9251
Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X9250 integrates 4 digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array though the switches. Power up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FN8165
Rev.3.00
August 29, 2006
•
•
•
•
•
BLOCK DIAGRAM
V
CC
V
SS
V+
V-
R
0
R
1
Wiper
Counter
Register
(WCR)
Pot 0
V
H0
/R
H0
R
0
R
1
Wiper
Counter
Register
(WCR)
V
H2
/R
H2
HOLD
CS
SCK
SO
SI
A0
A1
WP
R
2
R
3
V
L0
/R
L0
V
W0
/R
W0
R
2
R
3
Resistor
Array
Pot 2
V
L2
/R
L2
V
W2
/R
W2
Interface
and
Control
Circuitry
Data
8
V
W1
/R
W1
R
0
R
1
Wiper
Counter
Register
(WCR)
V
H1
/R
H1
R
0
R
1
Wiper
Counter
Register
(WCR)
V
W3
/R
W3
V
H3
/R
H3
R
2
R
3
Resistor
Array
Pot1
V
L1
/R
L1
R
2
R
3
Resistor
Array
Pot 3
V
L3
/R
H3
FN8165 Rev.3.00
August 29, 2006
Page 1 of 20
X9250
Ordering Information
PART NUMBER
X9250TS24I
X9250TS24IZ (Note)
X9250TV24I
X9250TV24IZ (Note)
X9250US24
X9250US24Z (Note)
X9250US24I
X9250US24IZ (Note)
X9250UV24I
X9250UV24IZ (Note)
X9250TS24-2.7
PART
MARKING
X9250TS I
X9250TS ZI
X9250TV I
X9250TV ZI
X9250US
X9250US Z
X9250US I
X9250US ZI
X9250UV I
X9250UV ZI
X9250TS F
-2.7 to 5.5
100
50
V
CC
LIMITS (V)
5 ±10%
POTENTIOMETER
ORGANIZATION (k)
100
TEMP. RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
-40 to +85
-40 to +85
50
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
PACKAGE
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil)
(Pb-free)
24 Ld TSSOP
(4.4mm)
24 Ld TSSOP
(4.4mm) (Pb-free)
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil)
(Pb-free)
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil)
(Pb-free)
24 Ld TSSOP
(4.4mm)
24 Ld TSSOP
(4.4mm) (Pb-free)
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil)
(Pb-free)
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil)
(Pb-free)
24 Ld TSSOP
(4.4mm)
24 Ld TSSOP
(4.4mm) (Pb-free)
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil)
(Pb-free)
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil)
(Pb-free)
24 Ld TSSOP
(4.4mm)
24 Ld TSSOP
(4.4mm) (Pb-free)
24 Ld TSSOP
(4.4mm)
24 Ld TSSOP
(4.4mm) (Pb-free)
PKG. DWG. #
M24.3
M24.3
MDP0044
MDP0044
M24.3
M24.3
M24.3
M24.3
MDP0044
MDP0044
M24.3
M24.3
M24.3
M24.3
MDP0044
MDP0044
M24.3
M24.3
M24.3
M24.3
MDP0044
MDP0044
MDP0044
MDP0044
X9250TS24Z-2.7 (Note) X9250TS ZF
X9250TS24I-2.7*
X9250TS24IZ-2.7*
(Note)
X9250TV24I-2.7
X9250TS G
X9250TS ZG
X9250TV G
X9250TV24IZ-2.7 (Note) X9250TV ZG
X9250US24-2.7*
X9250US F
X9250US24Z-2.7* (Note) X9250US ZF
X9250US24I-2.7
X9250US G
X9250US24IZ-2.7 (Note) X9250US ZG
X9250UV24-2.7
X9250UV F
X9250UV24Z-2.7 (Note) X9250UV ZF
X9250UV24I-2.7
X9250UV G
X9250UV24IZ-2.7 (Note) X9250UV ZG
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8165 Rev.3.00
August 29, 2006
Page 2 of 20
X9250
PIN DESCRIPTIONS
Serial Output (SO)
SO is a serial data output pin. During a read cycle, data
is shifted out on this pin. Data is clocked out by the
falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9250.
Chip Select (CS)
When CS is HIGH, the X9250 is deselected and the SO
pin is at high impedance, and (unless an internal write
cycle is underway) the device will be in the standby
state. CS LOW enables the X9250, placing it in the
active power mode. It should be noted that after a
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause the
serial communication with the controller without resetting
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH
at all times.
Device Address (A
0
-
A
1
)
The address inputs are used to set the least significant 2
bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with the
X9250. A maximum of 4 devices may occupy the SPI
serial bus.
Potentiometer Pins
V
H
/R
H
(V
H0
/R
H0
- V
H3
/R
H3
), V
L
/R
L
(V
L0
/R
L0
- V
L3
/R
L3
)
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer.
S0
A0
V
W3
/R
W3
V
H3
/R
H3
V
L3
/R
L3
V+
V
CC
V
L0
/R
L0
V
H0
/R
H0
V
W0
/R
W0
CS
WP
V
W
/R
W
(V
W0
/R
W0 -
V
W3
/R
W3
)
The wiper pins are equivalent to the wiper terminal of a
mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Analog Supplies (V+, V-)
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
PIN CONFIGURATION
SOIC/TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
X9250
24
23
22
21
20
19
18
17
16
15
14
13
HOLD
SCK
V
L2
/R
L2
V
H2
/R
L2
V
W2
/R
W2
V–
V
SS
V
W1
/R
W1
V
H1
/R
H1
V
L1
/R
L1
A1
SI
PIN NAMES
Symbol
SCK
SI, SO
A
0
-A
1
V
H0
/R
H0–
V
H3
/R
H3
,
V
L0
/R
L0–
V
L3
/R
L3
V
W0
/R
W0–
V
W3
/R
W3
WP
V+,V-
V
CC
V
SS
NC
Description
Serial Clock
Serial Data
Device Address
Potentiometer Pins
(terminal equivalent)
Potentiometer Pins
(wiper equivalent)
Hardware Write Protection
Analog Supplies
System Supply Voltage
System Ground
No Connection
FN8165 Rev.3.00
August 29, 2006
Page 3 of 20
X9250
DEVICE DESCRIPTION
Serial Interface
The X9250 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be LOW
and the HOLD and WP pins must be HIGH during the
entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9250 is comprised of four resistor arrays. Each
array contains 255 discrete resistive segments that are
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical
potentiometer (V
H
/R
H
and V
L
/R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V
W
/R
W
) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8 bits of the WCR are decoded to
select, and enable, one of 256 switches.
Wiper Counter Register (WCR)
The X9250 contains four Wiper Counter Registers, one
for each XDCP potentiometer. The WCR is equivalent to
a serial-in, parallel-out register/counter with its outputs
decoded to select one of 256 switches along its resistor
array. The contents of the WCR can be altered in four
ways: it may be written directly by the host via the write
Wiper Counter Register instruction (serial load); it may
be written indirectly by transferring the contents of one of
four associated Data Registers via the XFR Data
Register or Global XFR Data Register instructions
(parallel load); it can be modified one step at a time by
the increment/decrement instruction. Finally, it is loaded
with the contents of its Data Register zero (DR0) upon
power-up.
The Wiper Counter Register is a volatile register; that is,
its contents are lost when the X9250 is powered-down.
Although the register is automatically loaded with the
value in R0 upon power-up, this may be different from
the value present at power-down.
Data Registers
Each potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the Data
Registers is a nonvolatile operation and will take a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system
parameters or user preference data.
Data Register Detail
(MSB)
D7
NV
D6
NV
D5
NV
D4
NV
D3
NV
D2
NV
D1
NV
(LSB)
D0
NV
FN8165 Rev.3.00
August 29, 2006
Page 4 of 20
X9250
Figure 1. Detailed Potentiometer Block Diagram
(One of Four Arrays)
Serial Data Path
From Interface
Circuitry
Register 0
8
Register 1
8
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
Serial
Bus
Input
C
o
u
n
t
e
r
D
e
c
o
d
e
V
H
/R
H
Register 2
Register 3
If WCR = 00[H] then V
W
/R
W
= V
L
/R
L
If WCR = FF[H] then V
W
/R
W
= V
H
/R
H
UP/DN
Modified SCK
Inc/Dec
Logic
UP/DN
CLK
V
L
/R
L
V
W
/R
W
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by the
device. The progress of this internal write operation can
be monitored by a write in process bit (WIP). The WIP bit
is read with a read status command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9250 from the host, following
a CS going HIGH to LOW, is called the Identification
byte. The most significant four bits of the slave address
are a device type identifier, for the X9250 this is fixed as
0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one of
four devices on the bus. The physical device address is
defined by the state of the A
0
- A
1
input pins. The X9250
compares the serial data stream with the address input
state; a successful compare of both address bits is
required for the X9250 to successfully continue the
command sequence. The A
0
- A
1
inputs can be actively
driven by CMOS input signals or tied to V
CC
or V
SS
.
The remaining two bits in the slave byte must be set to 0.
The four high order bits of the instruction byte specify the
operation. The next two bits (R
1
and R
0
) select one of
the four registers that is to be acted upon when a
FN8165 Rev.3.00
August 29, 2006
Figure 2. Identification Byte Format
Device Type
Identifier
0
1
0
1
0
0
A1
A0
Device Address
Instruction Byte
The next byte sent to the X9250 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the four pots and, when applicable, they
point to one of four associated registers. The format is
shown below in Figure 3.
Figure 3. Instruction Byte Format
Register
Select
I3
I2
I1
I0
R1
R0
P1
P0
Instructions
Pot Select
register oriented instruction is issued. The last two bits
(P1 and P
0
) selects which one of the four potentiometers
is to be affected by the instruction.
Page 5 of 20
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