Intel
®
3 Series Express Chipset
Family
Datasheet
- For the Intel
®
82Q35, 82Q33, 82G33 Graphics and Memory
Controller Hub (GMCH) and Intel
®
82P35 Memory Controller
Hub (MCH)
August 2007
Document Number: 316966-002
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL
®
PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY
WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL
PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY,
OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended
for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from
future changes to them.
The Intel
®
82Q35 GMCH, 82Q33 GMCH, 82G33 GMCH, and 82P35 MCH may contain design defects or errors known as errata
which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was
developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips
Electronics N.V. and North American Philips Corporation.
Intel, Pentium, Intel Core, Intel Inside, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007, Intel Corporation. All rights reserved.
2
Datasheet
Contents
1
Introduction ...................................................................................................19
1.1
1.2
1.3
Terminology ........................................................................................24
Reference Documents ...........................................................................26
(G)MCH Overview.................................................................................27
1.3.1
Host Interface.........................................................................27
1.3.2
System Memory Interface.........................................................28
1.3.3
Direct Media Interface (DMI).....................................................29
1.3.4
PCI Express* Interface.............................................................29
1.3.5
Graphics Features (Intel
®
82Q35, 82Q33, 82G33 GMCH Only) .......30
1.3.6
SDVO and Analog Display Features (Intel
®
82Q35, 82Q33,
82G33 GMCH Only) .................................................................30
1.3.7
(G)MCH Clocking .....................................................................31
1.3.8
Thermal Sensor ......................................................................31
1.3.9
Power Management .................................................................32
1.3.10 Intel
®
Active Management Technology (Intel
®
AMT)/ Controller
Link (Intel
®
82Q35 GMCH Only) ................................................32
1.3.11 Intel
®
Trusted Execution Technology (Intel
®
82Q35 GMCH Only) .... 33
1.3.12 Intel
®
Virtualization Technology for Directed I/O (Intel
®
VT-d)
(Intel
®
82Q35 GMCH Only) .......................................................33
Host Interface Signals ...........................................................................36
System Memory (DDR2/DDR3) Channel A Interface Signals........................40
System Memory (DDR2/DDR3) Channel B Interface Signals........................41
System Memory DDR2/DDR3 Miscellaneous Signals .................................. 42
PCI Express* Interface Signals ...............................................................43
Controller Link Interface Signals .............................................................43
Analog Display Signals (Intel
®
82Q33, GMCH, 82Q33 GMCH, and 82G33
GMCH Only) ........................................................................................44
Clocks, Reset, and Miscellaneous ............................................................45
Direct Media Interface...........................................................................46
Serial DVO Interface (Intel
®
82Q35, 82Q33, 82G33 GMCH Only) ................. 47
Power and Grounds ..............................................................................50
2
Signal Description ...........................................................................................35
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
3
System Address Map .......................................................................................51
3.1
Legacy Address Range ..........................................................................55
3.1.1
DOS Range (0h – 9_FFFFh).......................................................56
3.1.2
Legacy Video Area (A_0000h – B_FFFFh) ....................................56
3.1.3
Expansion Area (C_0000h – D_FFFFh)........................................57
3.1.4
Extended System BIOS Area (E_0000h-E_FFFFh).........................57
3.1.5
System BIOS Area (F_0000h-F_FFFFh).......................................58
3.1.6
PAM Memory Area Details.........................................................58
Main Memory Address Range (1MB – TOLUD) ...........................................59
3.2.1
ISA Hole (15 MB-16 MB) ..........................................................60
3.2.2
TSEG.....................................................................................60
3.2.3
Pre-allocated Memory ..............................................................60
3
3.2
Datasheet
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
4
PCI Memory Address Range (TOLUD – 4GB) .............................................61
3.3.1
APIC Configuration Space (FEC0_0000h–FECF_FFFFh) ..................63
3.3.2
HSEG (FEDA_0000h–FEDB_FFFFh).............................................63
3.3.3
FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF) ................. 63
3.3.4
High BIOS Area.......................................................................63
Main Memory Address Space (4 GB to TOUUD) .........................................64
3.4.1
Memory Re-claim Background ...................................................65
3.4.2
Memory Reclaiming .................................................................65
PCI Express* Configuration Address Space...............................................65
PCI Express* Graphics Attach (PEG)........................................................66
Graphics Memory Address Ranges (Intel
®
82Q35, 82Q33, and 82G33
(G)MCH Only) ......................................................................................67
System Management Mode (SMM) ..........................................................67
3.8.1
SMM Space Definition ..............................................................68
3.8.2
SMM Space Restrictions............................................................68
3.8.3
SMM Space Combinations .........................................................69
3.8.4
SMM Control Combinations .......................................................69
3.8.5
SMM Space Decode and Transaction Handling..............................69
3.8.6
Processor WB Transaction to an Enabled SMM Address Space ........69
3.8.7
SMM Access through GTT TLB (Intel
®
82Q35, 82Q33, 82G33
GMCH Only) ...........................................................................70
Memory Shadowing ..............................................................................70
I/O Address Space................................................................................70
3.10.1 PCI Express* I/O Address Mapping ............................................71
(G)MCH Decode Rules and Cross-Bridge Address Mapping ..........................72
3.11.1 Legacy VGA and I/O Range Decode Rules ...................................72
Register Terminology ............................................................................74
Configuration Process and Registers ........................................................76
4.2.1
Platform Configuration Structure ...............................................76
Configuration Mechanisms .....................................................................77
4.3.1
Standard PCI Configuration Mechanism ......................................77
4.3.2
PCI Express* Enhanced Configuration Mechanism ........................77
Routing Configuration Accesses ..............................................................79
4.4.1
Internal Device Configuration Accesses.......................................80
4.4.2
Bridge Related Configuration Accesses........................................80
4.4.2.1
PCI Express* Configuration Accesses ........................... 80
4.4.2.2
DMI Configuration Accesses .......................................81
I/O Mapped Registers ...........................................................................81
4.5.1
CONFIG_ADDRESS—Configuration Address Register ..................... 81
4.5.2
CONFIG_DATA—Configuration Data Register ............................... 83
DRAM Controller (D0:F0).......................................................................85
5.1.1
VID—Vendor Identification........................................................87
5.1.2
DID—Device Identification ........................................................87
5.1.3
PCICMD—PCI Command ...........................................................88
5.1.4
PCISTS—PCI Status .................................................................89
5.1.5
RID—Revision Identification ......................................................90
5.1.6
CC—Class Code.......................................................................91
5.1.7
MLT—Master Latency Timer ......................................................91
5.1.8
HDR—Header Type ..................................................................92
Datasheet
(G)MCH Register Description ............................................................................73
4.1
4.2
4.3
4.4
4.5
5
DRAM Controller Registers (D0:F0)....................................................................85
5.1
4
5.2
SVID—Subsystem Vendor Identification......................................92
SID—Subsystem Identification ..................................................92
CAPPTR—Capabilities Pointer ....................................................93
PXPEPBAR—PCI Express* Egress Port Base Address .....................93
MCHBAR—(G)MCH Memory Mapped Register Range Base ..............94
GGC—GMCH Graphics Control Register (Intel
®
82Q35, 82Q33,
82G33 GMCH Only) .................................................................95
5.1.15 DEVEN—Device Enable.............................................................97
5.1.16 PCIEXBAR—PCI Express* Register Range Base Address ................99
5.1.17 DMIBAR—Root Complex Register Range Base Address ................ 101
5.1.18 PAM0—Programmable Attribute Map 0...................................... 102
5.1.19 PAM1—Programmable Attribute Map 1...................................... 104
5.1.20 PAM2—Programmable Attribute Map 2...................................... 105
5.1.21 PAM3—Programmable Attribute Map 3...................................... 106
5.1.22 PAM4—Programmable Attribute Map 4...................................... 107
5.1.23 PAM5—Programmable Attribute Map 5...................................... 108
5.1.24 PAM6—Programmable Attribute Map 6...................................... 109
5.1.25 LAC—Legacy Access Control.................................................... 110
5.1.26 REMAPBASE—Remap Base Address Register.............................. 111
5.1.27 REMAPLIMIT—Remap Limit Address Register ............................. 111
5.1.28 SMRAM—System Management RAM Control .............................. 112
5.1.29 ESMRAMC—Extended System Management RAM Control ............. 113
5.1.30 TOM—Top of Memory............................................................. 114
5.1.31 TOUUD—Top of Upper Usable Dram ......................................... 115
5.1.32 GBSM—Graphics Base of Stolen Memory................................... 116
5.1.33 BGSM—Base of GTT stolen Memory.......................................... 117
5.1.34 TSEGMB—TSEG Memory Base ................................................. 117
5.1.35 TOLUD—Top of Low Usable DRAM ............................................ 118
5.1.36 ERRSTS—Error Status ............................................................ 119
5.1.37 ERRCMD—Error Command ...................................................... 121
5.1.38 SMICMD—SMI Command........................................................ 122
5.1.39 SKPD—Scratchpad Data ......................................................... 122
5.1.40 CAPID0—Capability Identifier .................................................. 123
MCHBAR ........................................................................................... 127
5.2.1
CHDECMISC—Channel Decode Miscellaneous............................. 130
5.2.2
C0DRB0—Channel 0 DRAM Rank Boundary Address 0 ................. 131
5.2.3
C0DRB1—Channel 0 DRAM Rank Boundary Address 1 ................. 132
5.2.4
C0DRB2—Channel 0 DRAM Rank Boundary Address 2 ................. 133
5.2.5
C0DRB3—Channel 0 DRAM Rank Boundary Address 3 ................. 133
5.2.6
C0DRA01—Channel 0 DRAM Rank 0,1 Attribute ......................... 134
5.2.7
C0DRA23—Channel 0 DRAM Rank 2,3 Attribute ......................... 135
5.2.8
C0CYCTRKPCHG—Channel 0 CYCTRK PCHG............................... 135
5.2.9
C0CYCTRKACT—Channel 0 CYCTRK ACT ................................... 136
5.2.10 C0CYCTRKWR—Channel 0 CYCTRK WR ..................................... 137
5.2.11 C0CYCTRKRD—Channel 0 CYCTRK READ................................... 138
5.2.12 C0CYCTRKREFR—Channel 0 CYCTRK REFR ................................ 138
5.2.13 C0CKECTRL—Channel 0 CKE Control ........................................ 139
5.2.14 C0REFRCTRL—Channel 0 DRAM Refresh Control......................... 140
5.2.15 C0ODTCTRL—Channel 0 ODT Control ....................................... 142
5.2.16 C1DRB0—Channel 1 DRAM Rank Boundary Address 0 ................. 143
5.2.17 C1DRB1—Channel 1 DRAM Rank Boundary Address 1 ................. 143
5.2.18 C1DRB2—Channel 1 DRAM Rank Boundary Address 2 ................. 144
5.2.19 C1DRB3—Channel 1 DRAM Rank Boundary Address 3 ................. 144
5.2.20 C1DRA01—Channel 1 DRAM Rank 0,1 Attributes ........................ 145
5.2.21 C1DRA23—Channel 1 DRAM Rank 2,3 Attributes ........................ 145
5.1.9
5.1.10
5.1.11
5.1.12
5.1.13
5.1.14
Datasheet
5
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