R
Intel 915G/915GV/915GL/915P/
915PL/910GL Express Chipset
Datasheet
For the Intel
®
82915G/82915GV/82915GL/82910GL Graphics and
Memory Controller Hub (GMCH) and the Intel
®
82915P/82915PL
Memory Controller Hub (MCH)
®
February 2005
Document Number:
301467-005
R
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL
®
PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL
DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR
WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT,
COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining
applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
82915G,82915GV,82915GL,82910GL GMCH and 82915P/82915PL MCH may contain design defects or errors known as errata, which
may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Hyper-Threading Technology requires a computer system with an Intel® Pentium® 4 processor supporting HT Technology and a Hyper-Threading
Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See
http://www.intel.com/products/ht/hyperthreading_more.htm for more information including details on which processors support HT Technology.
Intel, Pentium, Celeron and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and
other countries.
*Other names and brands may be claimed as the property of others.
Copyright© 2004–2005, Intel Corporation. All rights reserved
1
2
Datasheet
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Contents
1
Introduction ....................................................................................................................... 17
1.1
1.2
1.3
Terminology.......................................................................................................... 24
Reference Documents.......................................................................................... 26
GMCH (MCH) Overview....................................................................................... 26
1.3.1
Host Interface........................................................................................ 26
1.3.2
System Memory Interface..................................................................... 27
1.3.3
Direct Media Interface (DMI)................................................................. 28
1.3.4
PCI Express* Graphics Interface (Intel
®
82915G/82915P/
and 82915PL Only) ............................................................................... 28
1.3.5
Integrated Graphics (Intel
®
82915G/82915GV/82910GL/82915GL
GMCH Only) ......................................................................................... 29
1.3.6
Analog and Intel
®
SDVO Displays (Intel
®
82915G/82915GV/82910GL/82915GL GMCH Only) ........................... 31
1.3.7
System Interrupts.................................................................................. 31
1.3.8
(G)MCH Clocking.................................................................................. 31
1.3.9
Power Management.............................................................................. 32
Host Interface Signals .......................................................................................... 35
DDR/DDR2 DRAM Channel A Interface .............................................................. 38
DDR/DDR2 DRAM Channel B Interface .............................................................. 39
DDR/DDR2 DRAM Reference and Compensation .............................................. 40
PCI Express* x16 Graphics Port Signals (Intel
®
82915G, 82915P,
82915PL Only)...................................................................................................... 41
Analog Display Signals (Intel
®
82915G/82915GV/82915GL/82910GL
GMCH Only) ......................................................................................................... 42
Clocks, Reset, and Miscellaneous ....................................................................... 43
Direct Media Interface (DMI) ................................................................................ 43
Intel
®
Serial DVO (SDVO) Interface (82915G/82915GV/82915GL/82910GL
GMCH Only) ......................................................................................................... 44
Power and Ground ............................................................................................... 45
Reset States and Pull-up/Pull-downs................................................................... 46
2
Signal Description ............................................................................................................. 33
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
3
Register Description.......................................................................................................... 53
3.1
3.2
3.3
Register Terminology ........................................................................................... 53
Platform Configuration.......................................................................................... 55
General Routing Configuration Accesses ............................................................ 58
3.3.1
Standard PCI Bus Configuration Mechanism ....................................... 58
3.3.2
Logical PCI Bus 0 Configuration Mechanism ....................................... 58
3.3.3
Primary PCI and Downstream Configuration Mechanism .................... 59
3.3.4
PCI Express* Enhanced Configuration Mechanism ............................. 60
3.3.5
Intel
®
915x GMCH Configuration Cycle Flowchart ............................... 62
I/O Mapped Registers .......................................................................................... 63
3.4.1
CONFIG_ADDRESS—Configuration Address Register ...................... 63
3.4
Datasheet
3
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3.4.2
4
4.1
CONFIG_DATA—Configuration Data Register .................................... 64
Host Bridge/DRAM Controller Registers (D0:F0) ............................................................. 65
Host Bridge/DRAM Controller PCI Register Details (D0:F0) ............................... 68
4.1.1
VID—Vendor Identification (D0:F0) ...................................................... 68
4.1.2
DID—Device Identification (D0:F0) ...................................................... 68
4.1.3
PCICMD—PCI Command (D0:F0) ....................................................... 69
4.1.4
PCISTS—PCI Status (D0:F0)............................................................... 70
4.1.5
RID—Revision Identification (D0:F0).................................................... 71
4.1.6
CC—Class Code (D0:F0) ..................................................................... 71
4.1.7
MLT—Master Latency Timer (D0:F0)................................................... 72
4.1.8
HDR—Header Type (D0:F0) ................................................................ 72
4.1.9
SVID—Subsystem Vendor Identification (D0:F0)................................. 72
4.1.10 SID—Subsystem Identification (D0:F0)................................................ 73
4.1.11 CAPPTR—Capabilities Pointer (D0:F0) ............................................... 73
4.1.12 EPBAR—Egress Port Base Address (D0:F0) ...................................... 74
4.1.13 MCHBAR—(G)MCH Memory Mapped Register Range Base Address
(D0:F0).................................................................................................. 75
4.1.14 PCIEXBAR—PCI Express* Register Range Base Address (D0:F0)
(Intel
®
82915G/82915P/82915PL Only)................................................ 76
4.1.15 DMIBAR—Root Complex Register Range Base Address (D0:F0) ...... 77
4.1.16 GGC—GMCH Graphics Control Register (D0:F0)
(82915G/82915GV/82915GL/82910GL GMCH only)........................... 78
4.1.17 DEVEN—Device Enable (D0:F0) ......................................................... 79
4.1.18 PAM0—Programmable Attribute Map 0 (D0:F0) .................................. 81
4.1.19 PAM1—Programmable Attribute Map 1 (D0:F0) .................................. 82
4.1.20 PAM2—Programmable Attribute Map 2 (D0:F0) .................................. 83
4.1.21 PAM3—Programmable Attribute Map 3 (D0:F0) .................................. 84
4.1.22 PAM4—Programmable Attribute Map 4 (D0:F0) .................................. 85
4.1.23 PAM5—Programmable Attribute Map 5 (D0:F0) .................................. 86
4.1.24 PAM6—Programmable Attribute Map 6 (D0:F0) .................................. 87
4.1.25 LAC—Legacy Access Control (D0:F0) ................................................. 88
4.1.26 TOLUD—Top of Low Usable DRAM (D0:F0) ....................................... 89
4.1.27 SMRAM—System Management RAM Control (D0:F0)........................ 90
4.1.28 ESMRAMC—Extended System Management RAM Control (D0:F0) .. 91
4.1.29 ERRSTS—Error Status (D0:F0) ........................................................... 92
4.1.30 ERRCMD—Error Command (D0:F0) ................................................... 93
4.1.31 SKPD—Scratchpad Data (D0:F0) ........................................................ 94
4.1.32 CAPID0—Capability Identifier (D0:F0) ................................................. 94
MCHBAR Register Details ................................................................................... 96
5.1.1
C0DRB0—Channel A DRAM Rank Boundary Address 0 .................... 96
5.1.2
C0DRB1—Channel A DRAM Rank Boundary Address 1 .................... 98
5.1.3
C0DRB2—Channel A DRAM Rank Boundary Address 2 .................... 98
5.1.4
C0DRB3—Channel A DRAM Rank Boundary Address 3 .................... 98
5.1.5
C0DRA0—Channel A DRAM Rank 0,1 Attribute ................................. 99
5.1.6
C0DRA2—Channel A DRAM Rank 2,3 Attribute ................................. 99
5.1.7
C0DCLKDIS—Channel A DRAM Clock Disable ................................ 100
5.1.8
C0BNKARC—Channel A DRAM Bank Architecture .......................... 101
5.1.9
C0DRT1—Channel A DRAM Timing Register ................................... 102
5.1.10 C0DRC0—Channel A DRAM Controller Mode 0 ............................... 104
5.1.11 C1DRB0—Channel B DRAM Rank Boundary Address 0 .................. 106
5
MCHBAR Registers .......................................................................................................... 95
5.1
4
Datasheet
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5.1.12
5.1.13
5.1.14
5.1.15
5.1.16
5.1.17
5.1.18
5.1.19
5.1.20
5.1.21
5.1.22
6
6.1
C1DRB1—Channel B DRAM Rank Boundary Address 1 .................. 106
C1DRB2—Channel B DRAM Rank Boundary Address 2 .................. 106
C1DRB3—Channel B DRAM Rank Boundary Address 3 .................. 106
C1DRA0—Channel B DRAM Rank 0,1 Attribute ............................... 106
C1DRA2—Channel B DRAM Rank 2,3 Attribute ............................... 107
C1DCLKDIS—Channel B DRAM Clock Disable ................................ 107
C1BNKARC—Channel B Bank Architecture ...................................... 107
C1DRT1—Channel B DRAM Timing Register 1 ................................ 107
C1DRC0—Channel B DRAM Controller Mode 0 ............................... 107
PMCFG—Power Management Configuration .................................... 108
PMSTS—Power Management Status ................................................ 108
EPBAR Registers—Egress Port Register Summary ...................................................... 109
EP RCRB Configuration Register Details .......................................................... 109
6.1.1
EPESD—EP Element Self Description............................................... 110
6.1.2
EPLE1D—EP Link Entry 1 Description .............................................. 111
6.1.3
EPLE1A—EP Link Entry 1 Address.................................................... 111
6.1.4
EPLE2D—EP Link Entry 2 Description .............................................. 112
6.1.5
EPLE2A—EP Link Entry 2 Address.................................................... 113
Direct Media Interface (DMI) RCRB Register Details ........................................ 116
7.1.1
DMIVCECH—DMI Virtual Channel Enhanced Capability Header ..... 116
7.1.2
DMIPVCCAP1—DMI Port VC Capability Register 1 .......................... 116
7.1.3
DMIPVCCAP2—DMI Port VC Capability Register 2 .......................... 117
7.1.4
DMIPVCCTL—DMI Port VC Control .................................................. 117
7.1.5
DMIVC0RCAP—DMI VC0 Resource Capability ................................ 118
7.1.6
DMIVC0RCTL0—DMI VC0 Resource Control ................................... 119
7.1.7
DMIVC0RSTS—DMI VC0 Resource Status....................................... 120
7.1.8
DMIVC1RCAP—DMI VC1 Resource Capability ................................ 120
7.1.9
DMIVC1RCTL1—DMI VC1 Resource Control ................................... 121
7.1.10 DMIVC1RSTS—DMI VC1 Resource Status....................................... 121
7.1.11 DMILCAP—DMI Link Capabilities ...................................................... 122
7.1.12 DMILCTL—DMI Link Control .............................................................. 122
7.1.13 DMILSTS—DMI Link Status ............................................................... 123
Host-PCI Express* Bridge PCI Register Details (D1:F0) ................................... 128
8.1.1
VID1—Vendor Identification (D1:F0) .................................................. 128
8.1.2
DID1—Device Identification (D1:F0) .................................................. 128
8.1.3
PCICMD1—PCI Command (D1:F0) ................................................... 129
8.1.4
PCISTS1—PCI Status (D1:F0)........................................................... 130
8.1.5
RID1—Revision Identification (D1:F0)................................................ 132
8.1.6
CC1—Class Code (D1:F0) ................................................................. 132
8.1.7
CL1—Cache Line Size (D1:F0) .......................................................... 133
8.1.8
HDR1—Header Type (D1:F0) ............................................................ 133
8.1.9
PBUSN1—Primary Bus Number (D1:F0) ........................................... 133
8.1.10 SBUSN1—Secondary Bus Number (D1:F0) ...................................... 134
8.1.11 SUBUSN1—Subordinate Bus Number (D1:F0) ................................. 134
8.1.12 IOBASE1—I/O Base Address (D1:F0) ............................................... 135
8.1.13 IOLIMIT1—I/O Limit Address (D1:F0) ................................................ 135
8.1.14 SSTS1—Secondary Status (D1:F0) ................................................... 136
8.1.15 MBASE1—Memory Base Address (D1:F0)........................................ 137
7
DMIBAR Registers—Direct Media Interface (DMI) RCRB ............................................. 115
7.1
8
Host-PCI Express* Bridge Registers (D1:F0) (Intel
®
82915G/82915P/82915PL Only) 125
8.1
Datasheet
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