Intel
®
82598 10 GbE Controller
Datasheet
LAN Access Division
FEATURES
General
Serial Flash Interface
4-wire SPI EEPROM Interface
Configurable LED operation for software or OEM
customization of LED displays
Protected EEPROM space for private configuration
Device disable capability
Package Size - 31 x 31 mm
Networking
Complies with the 10 Gb/s and 1 Gb/s Ethernet/802.3ap
(KX/KX4) specification
Complies with the 10 Gb/s Ethernet/802.3ae (XAUI)
specification
Complies with the 1000BASE-BX specification
Support for jumbo frames of up to 16 kB
Auto negotiation clause 73 for supported mode
CX4 per 802.3ak
Flow control support: send/receive pause frames and
receive FIFO thresholds
Statistics for management and RMON
802.1q VLAN Support
TCP Segmentation Offload (TSO): up to 256 kB
IPv6 support for IP/TCP and IP/UDP receive checksum
offload
Fragmented UDP checksum offload for packet
reassembly
Message Signaled Interrupts (MSI)
Message Signaled Interrupts (MSI-X)
Interrupt throttling control to limit maximum interrupt
rate and improve CPU usage
Multiple receive queues (RSS) 8 x 8 and 16 x 4
32 transmit queues
Dynamic interrupt moderation
DCA support
TCP timer interrupts
No snoop
Relaxed ordering
Support for 16 Virtual Machines Device queues (VMDq)
per port
Host Interface
PCI Express* (PCIe*) Specification v2.0 (2.5 GT/s)
Bus width - x1, x2, x4, x8
64-bit address support for systems using more than
four GB of physical memory
MAC F
UNCTIONS
Descriptor ring management hardware for transmit and
receive
ACPI register set and power down functionality supporting D0
and D3 states
A mechanism for delaying/reducing transmit interrupts
Software-controlled global reset bit (resets everything except
the configuration registers)
Eight Software-Definable Pins (SDP) per port
Four of the SDP pins can be configured as general-purpose
interrupts
Wakeup
IPv6 wake-up filters
Configurable flexible filter (through EEPROM)
LAN function disable capability
Programmable receive buffer of 512 kB, which can be
subdivided to up-to-eight individual packet buffers
Programmable transmit buffer of 320 kB, subdivided into up-
to-eight individual packet buffers of 40 kB each
Default Configuration by EEPROM for all LEDs for pre-driver
functionality
Manageability
Eight VLAN L2 filters
16 Flex L3 Port filters
Four flexible TCO filters
Four L3 address filters (IPv4)
Advanced pass through-compatible management packet
transmit/receive support
SMBus interface to an external BMC
NC-SI interface to an external BMC
Four L3 address filters (IPv6)
Four L2 address filters
Reference Number: 319282-007
Revision: 3.2
October 2010
Intel
®
82598 10 GbE Controller
Legal
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ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
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MAY OCCUR.
Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the
absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition
and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information
here is subject to change without notice. Do not finalize a design with this information.
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deviate from published specifications. Current characterized errata are available on request.
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*Other names and brands may be claimed as the property of others.
Copyright © 2008, 2009, 2010; Intel Corporation. All Rights Reserved.
Intel
®
82598 10 GbE Controller
Datasheet
2
Reference Number: 319282-007
Revision Number: 3.2
October 2010
Intel
®
82598 10 GbE Controller
Revisions
Rev
Date
Comments
• First integrated version.
• Added MUSIC and iSCSI TSO definition.
• Initialization chapter updated
• All main functions are integrated.
Chapters that are not updated:
• NVM memory Map.
• Manageability.
• Power management.
First full version. Too many changes to list here… Revision control indicates changes from
Zoar.
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Pin changes to support 4 more SDP (per port), POR Baypass, Clock Bypass, power pin
changes and number of Spares.
PCIe* read request size is limited to 256B
Removal of PCIe* Gen 2 support
Updated the initialization sequence for proper link setup at the different modes of
network interface
Sync up with Zoar C-spec 0.94
Many address changes in the programming interface
Ball out updated
Added Cibolo for the feature summary comparison
Changes in LAN/SAN use of RSS
Music chapter was updated, registers and statistics related to Music were updated
Added EEPROM to CSR capability
Link initialization was updated
Modified the Tx descriptors to be 8 per queue (instead of 4 and no global descriptors)
Added 10 general purpose semaphores
EEPORM PCIe* fields were re-organized, Added EEPROM words for MAC, Music
Jumbo frame support up to 16KB
Address changes in programming interface
0.75
08/05
0.89
10/05
0.9
11/05
Reference Number: 319282-007
Revision Number: 3.2
October 2010
Intel
®
82598 10 GbE Controller
Datasheet
3
Intel
®
82598 10 GbE Controller
Rev
Date
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Added the missing FC statistics
Added control bits for Music (Recycle mode, Receive LSP)
Added register A - packet types for packet split
Reference section updated
Pin names updated to mutch design
Updated Error field in the Rx descriptor
Udded a column to indicate for each register it internal block location (for internal use
only)
Added PBACL, TFCS, MREVID registers
Added missing bits in Music configuration
Added missing flow control statistics (were missing in the register description)
Removed PEJC register
Added documentation to missing PCIe* registers
Fixed old refrences to RCTL to the new Oplin registers
Changed the SDP control bits location (modified registers CTRL, EXT_CTRL and added
ESDP register)
Removed MPME abd MEN bits from EEPROM load and WUC, Added MEN bit for Port 1
in the EEPROM (word 0x38)
Only EEPROM section pointer of 0xFFFF will act as non valid pointer.
Removed LPE (bit 2) from FCRTL.
Added ADVD3WUC to WUC register and added an additional word to be read from the
EEPROM to load this bit value.
Removed BCN control and status registers (and any other documentation)
Changed the addresses of QPTC and QBRC
Added a note that EEPROM control words are loaded after PERST, inband reast or
LAN_PWR_GOOD
Removed interrupt statistics
Added Frimware EEPROM words to section 7
Removed SOL_on and IDE_on from FWSM register (reserved)
Fixed and added registers in the MAC section to support auto negotiation, DFT and
better descriptions
Added XEC stat (XSUM error) at 0x04120
Added a new mode in DESCTYPE to always use the header buffer in split header mode
Removed the fixed partition control bits for RX/TX PB partition and added the
RXPBSIZE/TXPBSIZE registers for PB partition
Removed BWG status registers
Changed the Rx status to MNG (PIF -> Reserved)
Removed SW initiated PAUSE transmission capability
0.95
01/06
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Intel
®
82598 10 GbE Controller
Datasheet
4
Reference Number: 319282-007
Revision Number: 3.2
October 2010
Intel
®
82598 10 GbE Controller
Rev
Date
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Comments
Offload for Rx Ipv6 packets with "home extention" or fragments were changed back to
No.
iSCSI support for Rx header split was removed (Oplin will not support this feature)
Fixed BSIZEHEADER to max at 1024 instead of 16KB as stated.
Chnaged the PCIe* analog section load time from LAN_PWR_GOOD to be after
PE_RST_N instead.
Removed No MNG SMBus configuration offset from the MNG test structure pointer.
Added RCLKEXTP/N clock characterization in the electrical section
Removed the promiscuous cases that stated that PIF bit will be cleared
Made bit 25 from "RSS Field Enable" in the MRQC register reserved 0.
Added the Pullups table (section 3.2)
Removed IPIDV bit from MNG status
Changed the default value of the MNG_en bit in the GRC register so that the MNG is
enabled by default
Added MNGTXMAP register that controls the mapping of the MNG transmit traffic to
the appropriate TC
Added a note that For proper operation PTHRESH value should be bigger than the
number of buffers needed to accommodate a single packet.
Removed Drop_En bit from RXDCTL and crerated 2 registers DROPEN0,1 that will hold
all drop enable bits (bit per queue).
Changed the addresses of the RNBC statistical counters
Added a bit to bypass the descriptor monitor in the RXCTRL
Added the limitation that in Music mode Rx buffers should be x2 in BSIZEPACKET
Added a bit in RDRXCTL to reflect that the DMA init is done, this bit was also added to
the SW initialization flow (to make sure software waits for DMA init done indication)
Removed line 0x13 in the packet types supported by packet split (duplicate to line
0x0)
Removed PSR_type0 as there is no L2 split
Changed the ATLASCTL register so it will support Atlas registers read
Added Atlas Tx-> Rx loopback
Added a note that under Music Jumbo frames support is restricted to 9KB.
Added a mode for TXPBSIZE to support diagnostics that enables the full Tx PB (320K)
as a single packet buffer.
Added an EEPROM word that enables the loading of AUTOC2 (upper half) from the
EEPROM.
Added a new statistics for Error byte count (0x04008)
Added bits in AUTOC that reflect the connection speed type (BX,KX,KX4,CX4,XAUI)
Changed the format of the "write configuration command" (BMC -> Oplin) to support
3 bytes of address instead of 2.
Chenged the format of the "read configuration request" (Oplin -> BMC) to support 3
bytes of address instead of 2.
Restricted BSIZEHEADER to 1K bytes
1.0
02/06
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Reference Number: 319282-007
Revision Number: 3.2
October 2010
Intel
®
82598 10 GbE Controller
Datasheet
5
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