21154 PCI-to-PCI Bridge
Datasheet
Product Features
s
s
s
s
s
s
s
s
s
Complies fully with the
PCI Local Bus
Specification,
Revision 2.1
Complies fully with the
PCI Power
Management Specification,
Revision 1.0
1
Supports 64-bit extension signals on the
primary and secondary interfaces
Implements delayed transactions for all PCI
configuration, I/O, and memory read
commands–up to three transactions
simultaneously in each direction
Allows 152 bytes of buffering (data and
address) for upstream posted memory write
commands and 88 bytes of buffering for
downstream posted memory write
commands—up to nine upstream and five
downstream posted write transactions
simultaneously
Allows 152 bytes of read data buffering
upstream and 152 bytes of read data
buffering downstream
Provides concurrent primary and secondary
bus operation to isolate traffic
Provides ten secondary clock outputs:
— Low skew, permitting direct drive of
option slots
— Individual clock disables, capable of
automatic configuration during reset
Provides arbitration support for nine
secondary bus devices:
— A programmable 2-level arbiter
— Hardware disable control, permitting use
of an external arbiter
s
s
s
s
s
s
s
s
Provides a 4-pin general-purpose I/O
interface, accessible through device-
specific configuration space
Provides enhanced address decoding:
— A 32-bit I/O address range
— A 32-bit memory-mapped I/O address
range
— A 64-bit prefetchable memory address
range
— ISA-aware mode for legacy support in
the first 64KB of I/O address range
— VGA addressing and VGA palette
snooping support
Includes live insertion support
Supports PCI transaction forwarding for the
following commands:
— All I/O and memory commands
— Type 1 to Type 1 configuration
commands
— Type 1 to Type 0 configuration
commands (downstream only)
— All Type 1 to special cycle configuration
commands
Includes downstream lock support
Supports both 5-V and 3.3-V signaling
environments
Available in both 33 MHz and 66 Mhz
versions
Provides an IEEE standard 1149.1 JTAG
interface
1.
For the 21154–AB and later revisions only. The 21154–AA does not implement this feature.
Order Number: 278108-002
July 1999
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 21154 PCI-to-PCI Bridge may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 1999
*Third-party brands and names are the property of their respective owners.
Datasheet
21154 PCI-to-PCI Bridge
Contents
1.0
Introduction......................................................................................................................... 1
1.1
1.2
Architecture ........................................................................................................... 3
Data Path .............................................................................................................. 5
1.2.1 Posted Write Queue ................................................................................. 6
1.2.2 Delayed Transaction Queue..................................................................... 6
1.2.3 Read Data Queue .................................................................................... 6
2.0
Signal Pins ......................................................................................................................... 7
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
Primary PCI Bus Interface Signals ........................................................................ 8
Primary PCI Bus Interface 64-Bit Extension Signals.......................................... 11
Secondary PCI Bus Interface Signals ................................................................. 12
Secondary PCI Bus Interface 64-Bit Extension Signals ...................................... 14
Secondary Bus Arbitration Signals...................................................................... 15
General-Purpose I/O Interface Signals ............................................................... 15
Clock Signals....................................................................................................... 16
Reset Signals ...................................................................................................... 16
Miscellaneous Signals......................................................................................... 17
JTAG Signals ...................................................................................................... 18
3.0
Pin Assignment ................................................................................................................ 19
3.1
3.2
Numeric Pin Assignment .....................................................................................20
Pins Listed in Alphabetic Order ........................................................................... 25
4.0
PCI Bus Operation ...........................................................................................................31
4.1
4.2
Types of Transactions ......................................................................................... 31
Address Phase .................................................................................................... 32
4.2.1 Single Address Phase ............................................................................ 32
4.2.2 Dual Address Phase............................................................................... 32
Device Select (DEVSEL#) Generation ................................................................ 33
Data Phase.......................................................................................................... 33
Write Transactions .............................................................................................. 33
4.5.1 Posted Write Transactions ..................................................................... 34
4.5.2 Memory Write and Invalidate Transactions ............................................ 35
4.5.3 Delayed Write Transactions ................................................................... 36
4.5.4 Write Transaction Address Boundaries .................................................. 38
4.5.5 Buffering Multiple Write Transactions..................................................... 38
4.5.6 Fast Back-to-Back Write Transactions ................................................... 39
Read Transactions .............................................................................................. 40
4.6.1 Prefetchable Read Transactions ............................................................ 40
4.6.2 Nonprefetchable Read Transactions...................................................... 40
4.6.3 Read Prefetch Address Boundaries ....................................................... 41
4.6.4 Delayed Read Requests ........................................................................ 41
4.6.5 Delayed Read Completion with Target................................................... 42
4.6.6 Delayed Read Completion on Initiator Bus ............................................ 42
Configuration Transaction ................................................................................... 46
4.7.1 Type 0 Access to the 21154 ................................................................... 46
4.7.2 Type 1 to Type 0 Translation..................................................................47
4.3
4.4
4.5
4.6
4.7
Datasheet
iii
21154 PCI-to-PCI Bridge
4.8
4.9
4.10
4.7.3 Type 1 to Type 1 Forwarding ................................................................. 48
4.7.4 Special Cycles........................................................................................ 49
64-Bit Operation .................................................................................................. 50
4.8.1 64-Bit and 32-Bit Transactions Initiated by the 21154............................ 50
4.8.2 Address Phase of 64-Bit Transactions ................................................... 50
4.8.3 Data Phase of 64-Bit Transactions ........................................................ 51
4.8.4 64-Bit Transactions Received by the 21154........................................... 51
4.8.5 64-Bit Extension Support During Reset.................................................. 52
Transaction Flow Through .................................................................................. 52
Transaction Termination ..................................................................................... 53
4.10.1 Master Termination Initiated by the 21154 ............................................. 54
4.10.2 Master Abort Received by the 21154 ..................................................... 54
4.10.3 Target Termination Received by the 21154 ........................................... 55
4.10.3.1Delayed Write Target Termination Response ........................... 56
4.10.3.2Posted Write Target Termination Response ............................. 56
4.10.3.3Delayed Read Target Termination Response ........................... 57
4.10.4 Target Termination Initiated by the 21154 ............................................. 59
4.10.4.1Target Retry .............................................................................. 59
4.10.4.2Target Disconnect ..................................................................... 60
4.10.4.3Target Abort .............................................................................. 60
5.0
Address Decoding ............................................................................................................61
5.1
5.2
Address Ranges.................................................................................................. 61
I/O Address Decoding ......................................................................................... 61
5.2.1 I/O Base and Limit Address Registers ................................................... 62
5.2.2 ISA Mode ............................................................................................... 63
Memory Address Decoding ................................................................................. 64
5.3.1 Memory-Mapped I/O Base and Limit Address Registers ....................... 65
5.3.2 Prefetchable Memory Base and Limit Address Registers ...................... 66
5.3.3 Prefetchable Memory 64-Bit Addressing Registers................................ 67
VGA Support ....................................................................................................... 68
5.4.1 VGA Mode.............................................................................................. 68
5.4.2 VGA Snoop Mode .................................................................................. 69
5.3
5.4
6.0
Transaction Ordering ....................................................................................................... 71
6.1
6.2
6.3
6.4
Transactions Governed by Ordering Rules ......................................................... 71
General Ordering Guidelines .............................................................................. 72
Ordering Rules .................................................................................................... 72
Data Synchronization .......................................................................................... 73
7.0
Error Handling .................................................................................................................. 75
7.1
7.2
Address Parity Errors .......................................................................................... 75
Data Parity Errors................................................................................................ 76
7.2.1 Configuration Write Transactions to 21154 Configuration Space .......... 76
7.2.2 Read Transactions ................................................................................. 76
7.2.3 Delayed Write Transactions ................................................................... 77
7.2.4 Posted Write Transactions ..................................................................... 79
Data Parity Error Reporting Summary ................................................................ 80
System Error (SERR#) Reporting ....................................................................... 85
7.3
7.4
iv
Datasheet
21154 PCI-to-PCI Bridge
8.0
Exclusive Access.............................................................................................................. 87
8.1
8.2
8.3
Concurrent Locks ................................................................................................ 87
Acquiring Exclusive Access Across the 21154....................................................87
Ending Exclusive Access .................................................................................... 88
9.0
PCI Bus Arbitration........................................................................................................... 91
9.1
9.2
Primary PCI Bus Arbitration ................................................................................ 91
Secondary PCI Bus Arbitration............................................................................ 91
9.2.1 Secondary Bus Arbitration Using the Internal Arbiter ............................. 91
9.2.2 Secondary Bus Arbitration Using an External Arbiter............................. 93
9.2.3 Bus Parking ............................................................................................93
10.0
General-Purpose I/O Interface ......................................................................................... 95
10.1
10.2
10.3
gpio Control Registers......................................................................................... 95
Secondary Clock Control.....................................................................................96
Live Insertion ....................................................................................................... 98
11.0
Clocks............................................................................................................................... 99
11.1
11.2
Primary and Secondary Clock Inputs ..................................................................99
Secondary Clock Outputs.................................................................................... 99
11.2.1 Disabling Unused Secondary Clock Outputs ....................................... 100
12.0
13.0
14.0
66-Mhz Operation........................................................................................................... 101
PCI Power Management ................................................................................................ 103
Reset .............................................................................................................................. 105
14.1
14.2
14.3
Primary Interface Reset..................................................................................... 105
Secondary Interface Reset................................................................................ 105
Chip Reset......................................................................................................... 106
15.0
Configuration Space Registers....................................................................................... 107
15.1
PCI-to-PCI Bridge Standard Configuration Registers ....................................... 108
15.1.1 Vendor ID Register—Offset 00h........................................................... 109
15.1.2 Device ID Register—Offset 02h ........................................................... 109
15.1.3 Primary Command Register—Offset 04h .............................................109
15.1.4 Primary Status Register—Offset 06h ................................................... 111
15.1.5 Revision ID Register—Offset 08h ........................................................ 112
15.1.6 Programming Interface Register—Offset 09h ......................................113
15.1.7 Subclass Code Register—Offset 0Ah ..................................................113
15.1.8 Base Class Code Register—Offset 0Bh............................................... 113
15.1.9 Cache Line Size Register—Offset 0Ch ................................................ 113
15.1.10 Primary Latency Timer Register—Offset 0Dh ......................................114
15.1.11 Header Type Register—Offset 0Eh...................................................... 114
15.1.12 Primary Bus Number Register—Offset 18h ......................................... 114
15.1.13 Secondary Bus Number Register—Offset 19h..................................... 115
15.1.14 Subordinate Bus Number Register—Offset 1Ah .................................. 115
15.1.15 Secondary Latency Timer Register—Offset 1Bh ................................. 115
15.1.16 I/O Base Address Register—Offset 1Ch .............................................. 116
15.1.17 I/O Limit Address Register—Offset 1Dh............................................... 116
15.1.18 Secondary Status Register—Offset 1Eh .............................................. 117
Datasheet
v
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
