®
X9269
Single Supply/Low Power/256-Tap/2-Wire Bus
Data Sheet
March 28, 2005
FN8173.1
Dual Digitally-Controlled (XDCP™)
Potentiometers
FEATURES
• Dual–Two separate potentiometers
• 256 resistor taps/pot–0.4% resolution
• 2-Wire Serial Interface for write, read, and
transfer operations of the potentiometer single
supply device
•
Wiper Resistance, 100Ω typical V
CC
= 5V
• 4 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position on
Power-up.
• Standby Current < 5µA Max
• 50kΩ, 100kΩ versions of End to End Pot
Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes per Bit per
Register
• 24-Lead SOIC, 24-Lead TSSOP
• Low Power CMOS
• Power Supply V
CC
= 2.7V to 5.5V
DESCRIPTION
The X9269 integrates 2 digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-Wire bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and a four nonvolatile Data Registers that can
be directly written to and read by the user. The
contents of the WCR controls the position of the wiper
on the resistor array though the switches. Powerup
recalls the contents of the default Data Register (DR0)
to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
V
CC
R
H0
R
H1
2-Wire
Bus
Interface
Address
Data
Status
Write
Read
Transfer
Inc/Dec
Bus
Interface
and Control
Control
Power-on Recall
Wiper Counter
Registers (WCR)
Data Registers
(DR0–DR3)
V
SS
R
W0
R
L0
R
W1
R
L1
50kΩ or 100kΩ versions
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9269
DETAILED FUNCTIONAL DIAGRAM
R
H0
R
L0
R
W0
V
CC
Power-on
Recall
R
0
R
1
Wiper
Counter
Register
(WCR)
Pot 0
SCL
SDA
A3
A2
A1
A0
WP
INTERFACE
AND
CONTROL
CIRCUITRY
R
2
R
3
50kΩ and 100kΩ
256-taps
8
Data
Power-on
Recall
R
0
R
1
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
R
2
R
3
V
SS
R
L1
R
H1
R
W1
CIRCUIT LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage
amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
• Control the gain in audio and home entertainment
systems
• Provide the variable DC bias for tuners in RF
wireless systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
2
FN8173.1
March 28, 2005
X9269
PIN CONFIGURATION
SOIC/TSSOP
NC
A0
NC
NC
NC
NC
V
CC
R
L0
R
H0
R
W0
A2
WP
1
2
3
4
5
6
7
8
9
10
11
12
X9269
24
23
22
21
20
19
18
17
16
15
14
13
A3
SCL
NC
NC
NC
NC
V
SS
R
W1
R
H1
R
L1
A1
SDA
PIN ASSIGNMENTS
Pin
(SOIC/TSSOP)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Symbol
NC
A0
NC
NC
NC
NC
V
CC
R
L0
R
H0
R
W0
A2
WP
SDA
A1
R
L1
R
H1
R
W1
V
SS
NC
NC
NC
NC
SCL
A3
No Connect
Device Address for 2-Wire bus.
No Connect
No Connect
No Connect
No Connect
System Supply Voltage
Low Terminal for Potentiometer 0.
High Terminal for Potentiometer 0.
Wiper Terminal for Potentiometer 0.
Device Address for 2-Wire bus.
Hardware Write Protect
Function
Serial Data Input/Output for 2-Wire bus.
Device Address for 2-Wire bus.
Low Terminal for Potentiometer 1.
High Terminal for Potentiometer 1.
Wiper Terminal for Potentiometer 1.
System Ground
No Connect
No Connect
No Connect
No Connect
Serial Clock for 2-Wire bus.
Device Address for 2-Wire bus.
3
FN8173.1
March 28, 2005
X9269
PIN DESCRIPTIONS
Bus Interface Pins
S
ERIAL
D
ATA
I
NPUT
/O
UTPUT
(SDA)
The SDA is a bidirectional serial data input/output pin
for a 2-Wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-Wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of the
serial clock SCL.
It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the
guidelines for calculating typical values on the bus
pull-up resistors graph.
S
ERIAL
C
LOCK
(SCL)
This input is used by 2-Wire master to supply 2-Wire
serial clock to the X9269.
D
EVICE
A
DDRESS
(A3 - A0)
The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9269. A maximum of 16 devices may occupy the
2-Wire serial bus.
N
O
C
ONNECT
No connect pins should be left open. This pins are
used for Intersil manufacturing and testing purposes.
H
ARDWARE
W
RITE
P
ROTECT
I
NPUT
(WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer. Since
there are 2 potentiometers, there are 2 sets of R
H
and
R
L
such that R
H0
and R
L0
are the terminals of POT 0
and so on.
R
W
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4
potentiometers, there are 2 sets of R
W
such that R
W0
is the terminal of POT 0 and so on.
Bias Supply Pins
S
YSTEM
S
UPPLY
V
OLTAGE
(V
CC
)
AND
S
UPPLY
G
ROUND
(V
SS
)
The V
CC
pin is the system supply voltage. The V
SS
pin is the system ground.
Other Pins
4
FN8173.1
March 28, 2005
X9269
PRINCIPLES OF OPERATION
The X9269 is a integrated microcircuit incorporating
four resistor arrays and their associated registers and
counters and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometers. This section provides detail
description of the following:
– Resistor Array Description
– Serial Interface Description
– Instruction and Register Description.
Array Description
The X9269 is comprised of a resistor array (See Figure
1). Each array contains 255 discrete resistive segments
that are connected in series. The physical ends of each
array are equivalent to the fixed terminals of a
mechanical potentiometer (R
H
and R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R
W
) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).
The WCR may be written directly. These Data
Registers can the WCR can be read and written by the
host system.
Power-up and Down Requirements.
There are no restrictions on the power-up or power-
down conditions of V
CC
and the voltages applied to
the potentiometer pins provided that V
CC
is always
more positive than or equal to V
H
, V
L
, and V
W
, i.e.,
V
CC
≥
V
H
, V
L
, V
W
. The V
CC
ramp rate specification is
always in effect.
Figure 1. Detailed Potentiometer Block Diagram
One of Two Potentiometers
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
8
REGISTER 1
(DR1)
8
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR)
INC/DEC
LOGIC
UP/DN
MODIFIED SCL
UP/DN
CLK
R
L
SERIAL
BUS
INPUT
C
O
U
N
T
E
R
D
E
C
O
D
E
R
H
REGISTER 2
(DR2)
REGISTER 3
(DR3)
IF WCR = 00[H] THEN R
W
= R
L
IF WCR = FF[H] THEN R
W
= R
H
R
W
5
FN8173.1
March 28, 2005
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