Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the four I/O
pins (I/O
0
through I/O
3
) is then written into the location
specified on the address pins (A
0
through A
19
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The four input/output pins (I/O
0
through I/O
3
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1046CV33 is available in a standard 400-mil-wide
32-pin SOJ package with center power and ground (revolu-
tionary) pinout.
Functional Description
[1]
The CY7C1046CV33 is a high-performance CMOS static
RAM organized as 1,048,576 words by 4 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers.
Logic Block Diagram
Pin Configuration
SOJ
Top View
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
INPUT BUFFER
I/O
0
SENSE AMPS
1M x 4
ARRAY
I/O
1
I/O
2
I/O
3
CE
WE
OE
COLUMN
DECODER
POWER
DOWN
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
V
CC
GND
I/O
1
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
19
A
18
A
17
A
16
A
15
OE
I/O
3
GND
V
CC
I/O
2
A
14
A
13
A
12
A
11
A
10
NC
ROW DECODER
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
-8
[2]
8
100
10
-10
10
90
10
-12
12
85
10
-15
15
80
10
Unit
ns
mA
mA
Notes:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
2. Shaded areas contain advance information.
Cypress Semiconductor Corporation
Document #: 38-05003 Rev. *A
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 13, 2002
CY7C1046CV33
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[3]
.... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State
[3]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[3]
.................................–0.5V to V
CC
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Latch-up Current..................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to + 85°C
V
CC
3.0V – 3.6V
3.0V – 3.6V
DC Electrical Characteristics
Over the Operating Range
-8
[2]
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Test Conditions
Output HIGH Voltage V
CC
= Min., I
OH
= –4.0 mA
Output LOW Voltage V
CC
= Min., I
OL
= 8.0 mA
Input HIGH Voltage
Input LOW Voltage
[3]
Input Load Current
Output Leakage
Current
V
CC
Operating
Supply Current
GND < V
I
< V
CC
GND < V
OUT
< V
CC
,
Output Disabled
V
CC
= Max.,
f = f
MAX
= 1/t
RC
2.0
–0.3
–1
–1
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
100
40
2.0
–0.3
–1
–1
2.4
0.4
V
CC
2.0
+ 0.3
0.8
+1
+1
90
40
–0.3
–1
–1
-10
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
85
40
2.0
–0.3
–1
–1
-12
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
80
40
-15
V
V
V
V
µA
µA
mA
mA
Min. Max. Min. Max. Min. Max. Min. Max. Unit
I
SB2
Automatic CE
Max. V
CC
, CE > V
IH
Power-Down Current V
IN
> V
IH
or
—TTL Inputs
V
IN
< V
IL
, f = f
MAX
Automatic CE
Max. V
CC
,
Commercial
Power-Down Current CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
—CMOS Inputs
or V
IN
< 0.3V,
f=0
10
10
10
10
mA
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
= 3.3V
Max.
6
6
Unit
pF
pF
Notes:
3. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05003 Rev. *A
Page 2 of 9
CY7C1046CV33
AC Test Loads and Waveforms
[5]
8-, 10-ns devices:
OUTPUT
50
Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
12-, 15-ns devices:
3.3V
Z=50
Ω
R 317Ω
30 pF*
OUTPUT
30 pF
R2
351Ω
(a)
(b)
High-Z characteristics:
R 317Ω
3.0V
90%
GND
10%
ALL INPUT PULSES
90%
10%
3.3V
OUTPUT
5 pF
R2
351Ω
Rise Time: 1 V/ns
(c)
Fall Time: 1 V/ns
(d)
Notes:
5. AC characteristics (except High-Z) for all 8-ns and 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the
Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
Document #: 38-05003 Rev. *A
Page 3 of 9
CY7C1046CV33
AC Switching Characteristics
[6]
Over the Operating Range
-8
[2]
-10
-12
-15
Parameter
Read Cycle
t
power[7]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Description
V
CC
(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[9]
OE HIGH to High-Z
[8, 9]
CE LOW to Low-Z
[9]
CE HIGH to High-Z
[8, 9]
CE LOW to Power-up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[9]
WE LOW to High-Z
[8, 9]
Min.
1
8
Max.
Min.
1
10
Max.
Min.
1
12
Max.
Min.
1
15
Max.
Unit
µs
ns
8
3
8
4
0
4
3
4
0
8
8
6
6
0
0
6
4
0
3
4
10
7
7
0
0
7
5
0
3
0
3
0
3
10
3
10
5
0
5
3
5
0
10
12
8
8
0
0
8
6
0
3
5
12
3
12
6
0
6
3
6
0
12
15
10
10
0
0
10
7
0
3
6
15
15
7
7
7
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
[10, 11]
7
ns
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
7. t
POWER
gives the minimum amount of time that the power supply should be at stable, typical Vcc values until the first memory access can be performed.
8. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
9. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
10. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of
either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the Write.
11. The minimum Write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05003 Rev. *A
Page 4 of 9
CY7C1046CV33
s
Switching Waveforms
Read Cycle No. 1
[14, 15]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
[15, 16]
ADDRESS
t
RC
CE
t
ACE
OE
t
DOE
t
LZOE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZOE
t
HZCE
DATA VALID
t
PD
50%
I
SB
I
CC
HIGH
IMPEDANCE
DATA OUT
Notes:
12. t
r
< 3 ns for the -10, -12, and -15 speeds.
13. No input may exceed V
CC
+ 0.5V.
14. Device is continuously selected. OE, CE = V
IL
.
15. WE is HIGH for Read cycle.
16. Address valid prior to or coincident with CE transition LOW.
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