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CY7C136-35JIT

产品描述Dual-Port SRAM, 2KX8, 35ns, CMOS, PQCC52, PLASTIC, LCC-52
产品类别存储    存储   
文件大小463KB,共15页
制造商Cypress(赛普拉斯)
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CY7C136-35JIT概述

Dual-Port SRAM, 2KX8, 35ns, CMOS, PQCC52, PLASTIC, LCC-52

CY7C136-35JIT规格参数

参数名称属性值
厂商名称Cypress(赛普拉斯)
零件包装代码LCC
包装说明QCCJ,
针数52
Reach Compliance Codeunknown
ECCN代码EAR99
最长访问时间35 ns
其他特性AUTOMATIC POWER-DOWN; INTERRUPT FLAG
JESD-30 代码S-PQCC-J52
长度19.1262 mm
内存密度16384 bit
内存集成电路类型DUAL-PORT SRAM
内存宽度8
功能数量1
端口数量2
端子数量52
字数2048 words
字数代码2000
工作模式ASYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织2KX8
输出特性3-STATE
可输出YES
封装主体材料PLASTIC/EPOXY
封装代码QCCJ
封装形状SQUARE
封装形式CHIP CARRIER
并行/串行PARALLEL
认证状态Not Qualified
座面最大高度5.08 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子形式J BEND
端子节距1.27 mm
端子位置QUAD
宽度19.1262 mm

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CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
2K x 8 Dual-Port Static RAM
Features
Functional Description
The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146
are high speed CMOS 2K x 8 dual-port static RAMs. Two ports
are provided to permit independent access to any location in
memory. The CY7C132, CY7C136, and CY7C136A can be used
as either a standalone 8-bit dual-port static RAM or as a
MASTER dual-port RAM, in conjunction with the
CY7C142/CY7C146 SLAVE dual-port device. They are used in
systems that require 16-bit or greater word widths. This is the
solution to applications that require shared or buffered data, such
as cache memory for DSP, bit-slice, or multiprocessor designs.
Each port has independent control pins; chip enable (CE), write
enable (R/W), and output enable (OE). BUSY flags are provided
on each port. In addition, an interrupt flag (INT) is provided on
each port of the 52-pin PLCC version. BUSY signals that the port
is trying to access the same location currently being accessed
by the other port. On the PLCC version, INT is an interrupt flag
indicating that data is placed in an unique location (7FF for the
left port and 7FE for the right port).
An automatic power down feature is controlled independently on
each port by the chip enable (CE) pins.
True dual-ported memory cells that enable simultaneous reads
of the same memory location
2K x 8 organization
0.65 micron CMOS for optimum speed and power
High speed access: 15 ns
Low operating power: I
CC
= 110 mA (maximum)
Fully asynchronous operation
Automatic power down
Master CY7C132/CY7C136/CY7C136A
[1]
easily expands data
bus width to 16 or more bits using slave CY7C142/CY7C146
BUSY output flag on CY7C132/CY7C136/CY7C136A;
BUSY input on CY7C142/CY7C146
INT flag for port to port communication (52-Pin PLCC/PQFP
versions)
CY7C136, CY7C136A, and CY7C146 available in 52-pin
PLCC and 52-pin PQFP packages
Pb-free packages available
Logic Block Diagram
R/W
L
CE
L
OE
L
R/W
R
CE
R
OE
R
I/O
7L
I/O
0L
BUSY
L
I/O
CONTROL
I/O
CONTROL
I/O
7R
I/O
0R
BUSY
R
[2]
MEMORY
ARRAY
[2]
A
10L
A
0L
ADDRESS
DECODER
ADDRESS
DECODER
A
10R
A
0R
CE
L
OE
L
R/W
L
INT
L
[3]
ARBITRATION
LOGIC
(7C132/7C136 ONLY)
AND
INTERRUPTLOGIC
(7C136/7C146 ONLY)
CE
R
OE
R
R/W
R
INT
R
[3]
Notes
1. CY7C136 and CY7C136A are functionally identical.
2. CY7C132/CY7C136/CY7C136A (Master): BUSY is open drain output and requires pull up resistor. CY7C142/CY7C146 (Slave): BUSY is input.
3. Open drain outputs; pull up resistor required.
Cypress Semiconductor Corporation
Document #: 38-06031 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised March 24, 2009
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