Intel® 41210 Serial to Parallel PCI Bridge
Datasheet
Product Features
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PCI Express Specification,
Revision 1.0a
Support for single x8, single x4 or single x1
PCI Express operation.
64-bit addressing support
32-bit CRC (cyclic redundancy checking)
covering all transmitted data packets.
16-bit CRC on all link message
information.
Raw bit-rate on the data pins of 2.5 Gbit/s,
resulting in a raw bandwidth per pin of
250 MB/s.
Maximum realized bandwidth on PCI
Express interface is 2 GB/s (in x8 mode) in
each direction simultaneously, for an
aggregate of 4 GB/s.
PCI Local Bus Specification,
Revision 2.3.
PCI-to-PCI Bridge Specification,
Revision 1.1.
PCI-X Addendum to the PCI Local Bus
Specification,
Revision 1.0b
64-bit 66 MHz, 3.3 V, NOT 5 V tolerant.
On Die Termination (ODT) with 8.3KOhm
pull-up to 3.3V for PCI signals.
Six external REQ/GNT Pairs for internal
arbiter on segment A and B respectively.
Programmable bus parking on either the
last agent or always on the 41210 Bridge
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2-level programmable round-robin internal
arbiter with Multi-Transaction Timer
(MTT)
External PCI clock-feed support for
asynchronous primary and secondary
domain operation.
64-bit addressing for upstream and
downstream transactions
Downstream LOCK# support.
No upstream LOCK# support.
PCI fast Back-to-Back capable as target.
Up to four active and four pending
upstream memory read transactions
Up to two downstream delayed (memory
read, I/O read/write and configuration read/
write) transaction.
Tunable inbound read prefetch algorithm
for PCI MRM/MRL commands
Device hiding support for secondary PCI
devices.
Secondary bus Private Memory support via
Opaque memory region
Local initialization via SMBus
Secondary side initialization via Type 0
configuration cycles.
Full peer-to-peer read/write capability
between the two secondary PCI segments.
Order Number: 278875-005US
May 2005
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The Intel® 41210 Serial to Parallel PCI Bridge may contain design defects or errors known as errata which may cause the product to deviate from
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Copyright © 2005, Intel Corporation
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Contents
Contents
1
Introduction....................................................................................................................................
7
1.1
1.2
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4
4.1
4.2
4.3
4.4
About This Document ........................................................................................................... 7
Product Overview ................................................................................................................. 7
On Die Termination (ODT).................................................................................................... 8
PCI Express Interface.........................................................................................................10
PCI Bus Interface (Two Instances) .....................................................................................10
PCI Bus Interface 64-Bit Extension (Two Interfaces) .........................................................12
PCI Bus Interface Clocks and, Reset and Power Management (Two Interfaces) ..............13
Interrupt Interface (Two Interfaces) ....................................................................................13
Reset Straps .......................................................................................................................13
SMBus Interface .................................................................................................................15
Miscellaneous Pins .............................................................................................................15
DC Voltage and Current Specifications ..............................................................................17
AC Specifications................................................................................................................25
Voltage Filter Specifications ...............................................................................................27
VCC15 and VCC33 Voltage Requirements ........................................................................27
Timing Specifications ..........................................................................................................28
41210 Bridge Power Consumption .....................................................................................36
Power Delivery Guidelines..................................................................................................37
Reference and Compensation Pins ....................................................................................37
Thermal Specifications .......................................................................................................38
Package Specification ........................................................................................................40
Ball Map ..............................................................................................................................42
Signal List, sorted by Ball Location.....................................................................................44
Signal List, sorted by Signal Name.....................................................................................48
Signal Description
......................................................................................................................... 8
Electrical and Thermal Characteristics
.....................................................................................17
Package Specification and Ballout
............................................................................................40
Figures
1
2
3
4
5
6
7
8
9
10
Minimum Transmitter Timing and Voltage Output Compliance Specification.............................22
Compliance Test/Measurement Load.........................................................................................23
Minimum Receiver Eye Timing and Voltage Compliance Specification .....................................23
Voltage Requirements VCC33 versus VCC15 ...........................................................................27
PCI Output Timing ......................................................................................................................31
PCI Input Timing .........................................................................................................................31
PCI-X 3.3V Clock Waveform ......................................................................................................33
41210 Bridge Reference and Compensation Circuit Implementations .......................................38
41210 Bridge Package Dimensions (Top View) .........................................................................40
41210 Bridge Package Dimensions (Side View) ........................................................................41
3
Contents
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
ODT Signals ................................................................................................................................. 9
PCI Express Interface Pins......................................................................................................... 10
PCI Interface Pins....................................................................................................................... 11
PCI Interface Pins: 64-Bit Extensions......................................................................................... 12
PCI Clock and Reset Pins .......................................................................................................... 13
Interrupt Interface Pins ............................................................................................................... 13
Reset Strap Pins......................................................................................................................... 14
SMBus Interface Pins ................................................................................................................. 15
Miscellaneous Pins ..................................................................................................................... 15
Intel® 41210 Bridge DC Voltage Specifications ......................................................................... 17
DC Characteristics Input Signal Association .............................................................................. 18
DC Input Characteristics............................................................................................................. 18
DC Characteristic Output Signal Association ............................................................................. 18
DC Output Characteristic............................................................................................................ 19
Differential Transmitter (TX) DC Output Specifications .............................................................. 19
Differential Receiver (RX) DC Input Specifications .................................................................... 21
DC Specifications for PCI and PCI-X 3.3 V Signaling ................................................................ 24
DC Specification for Input Clock Signals .................................................................................... 25
DC Specification for Output Clock Signals ................................................................................. 25
Conventional PCI 3.3V AC Characteristics ................................................................................ 25
PCI-X 3.3V AC Characteristics ................................................................................................... 26
Differential Transmitter (TX) AC Output Specifications .............................................................. 28
Differential Receiver (RX) AC Input Specifications..................................................................... 29
PCI Interface Timing................................................................................................................... 30
PCI-X 3.3V Signal Timing Parameters ....................................................................................... 31
PCI and PCI-X Clock Timings .................................................................................................... 33
41210 Bridge Clock Timings....................................................................................................... 35
41210 Bridge Maximum Voltage Plane Currents ....................................................................... 37
41210 Bridge Thermal Voltage Plane Currents .......................................................................... 37
41210 Bridge Thermal Specifications ......................................................................................... 39
Signal List, sorted by Ball Name................................................................................................. 44
Signal List, sorted by Signal Name............................................................................................. 48
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Contents
Revision History
Date
May 2005
April 2005
September 2004
June 2004
September 2003
Revision
005
004
003
002
001
Description
Revised
Table 1, Table 9,
and
Section 3.8
Revised
Table 26 “PCI and PCI-X Clock Timings” on page 33
CLK Cycle Time parameters
Revised first page PCI Express operation description; updated information in Table 2.
Added Chapter 2. Removed original Sections 3.6 and 3.7. Updated VCC information to
VCC15.
Initial release
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