Mobile Intel
®
Celeron
®
Processor
on .13 Micron Process and in
Micro-FCPGA Package
Datasheet
April 2005
Document Number: 251308-008
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AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS
OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO
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Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Mobile Intel
®
Celeron
®
processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Celeron, Pentium, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and
other countries.
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Copyright © 2002–2005, Intel Corporation. All rights reserved.
2
Datasheet
Contents
1
Introduction...................................................................................................................................... 9
1.1
1.2
2
2.1
2.2
2.3
Terminology ........................................................................................................................ 10
References ......................................................................................................................... 10
FSB and GTLREF............................................................................................................... 11
Power and Ground Pins...................................................................................................... 11
Decoupling Guidelines........................................................................................................ 11
2.3.1 VCC Decoupling .................................................................................................... 12
2.3.2 FSB AGTL+ Decoupling ........................................................................................ 12
2.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking ................................................... 12
Voltage Identification and Power Sequencing .................................................................... 13
2.4.1 Phase Lock Loop (PLL) Power and Filter .............................................................. 14
2.4.2 Catastrophic Thermal Protection ........................................................................... 16
Signal Terminations, Unused Pins and TESTHI[11:0] ........................................................ 16
FSB Signal Groups ............................................................................................................. 18
Asynchronous GTL+ Signals ..............................................................................................20
Test Access Port (TAP) Connection ................................................................................... 20
FSB Frequency Select Signals (BSEL[1:0]) ....................................................................... 20
Maximum Ratings ............................................................................................................... 21
Processor DC Specifications ..............................................................................................21
AGTL+ FSB Specifications ................................................................................................. 29
FSB AC Specifications........................................................................................................ 30
Processor AC Timing Waveforms....................................................................................... 35
FSB Clock (BCLK) Signal Quality Specifications and Measurement Guidelines................ 45
FSB Signal Quality Specifications and Measurement Guidelines ...................................... 46
FSB Signal Quality Specifications and Measurement Guidelines ...................................... 49
3.3.1 Overshoot/Undershoot Guidelines......................................................................... 49
3.3.2 Overshoot/Undershoot Magnitude ......................................................................... 49
3.3.3 Overshoot/Undershoot Pulse Duration .................................................................. 49
3.3.4 Activity Factor ........................................................................................................ 50
3.3.5 Reading Overshoot/Undershoot Specification Tables ........................................... 50
3.3.6 Conformance Determination to Overshoot/Undershoot Specifications.................. 51
Processor Pinout ................................................................................................................ 59
Mobile Intel
®
Celeron
®
Processor Pin Assignments........................................................... 61
Alphabetical Signals Reference .......................................................................................... 75
Thermal Specifications ....................................................................................................... 84
6.1.1 Thermal Diode ....................................................................................................... 84
6.1.2 Thermal Monitor..................................................................................................... 85
Electrical Specifications ................................................................................................................. 11
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
3
3.1
3.2
3.3
FSB Signal Quality Specifications ................................................................................................. 45
4
5
Package Mechanical Specifications ..............................................................................................55
4.1
5.1
5.2
Pin Listing and Signal Definitions .................................................................................................. 61
6
Thermal Specifications and Design Considerations ...................................................................... 83
6.1
Datasheet
7
Configuration and Low Power Features ........................................................................................ 87
7.1
7.2
Power-On Configuration Options........................................................................................ 87
Clock Control and Low Power States ................................................................................. 87
7.2.1 Normal State.......................................................................................................... 87
7.2.2 AutoHALT Powerdown State ................................................................................. 88
7.2.3 Stop-Grant State.................................................................................................... 88
7.2.4 HALT/Grant Snoop State....................................................................................... 89
7.2.5 Sleep State ............................................................................................................ 89
7.2.6 Deep Sleep State................................................................................................... 90
Logic Analyzer Interface (LAI) ............................................................................................ 91
8.1.1 Mechanical Considerations.................................................................................... 91
8.1.2 Electrical Considerations ....................................................................................... 91
8
Debug Tools Specifications ........................................................................................................... 91
8.1
4
Datasheet
Figures
1
2
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4
5
6
7
8
9
10
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12
13
14
15
16
17
18
19
20
21
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27
28
29
30
31
32
33
VCCVID Pin Voltage and Current Requirements ....................................................................... 13
Typical VCCIOPLL, VCCA and VSSA Power Distribution.......................................................... 15
Phase Lock Loop (PLL) Filter Requirements............................................................................. 16
Illustration of VCC Static and Transient Tolerances (VID = 1.30 V ............................................ 24
Illustration of Deep Sleep VCC Static and Transient Tolerances (VID Setting = 1.30 V ............ 25
ITPCLKOUT[1:0] Output Buffer Diagram.................................................................................... 29
AC Test Circuit............................................................................................................................ 36
TCK Clock Waveform ................................................................................................................. 36
Differential Clock Waveform ....................................................................................................... 37
Differential Clock Crosspoint Specification ................................................................................. 37
FSB Common Clock Valid Delay Timings .................................................................................. 38
FSB Reset and Configuration Timings ....................................................................................... 38
Source Synchronous 2X (Address) Timings............................................................................... 39
Source Synchronous 4X Timings ............................................................................................... 40
Power Up Sequence.................................................................................................................. 41
Power Down Sequence .............................................................................................................. 42
Test Reset Timings..................................................................................................................... 42
THERMTRIP# to Vcc Timing ...................................................................................................... 42
FERR#/PBE# Valid Delay Timing............................................................................................... 43
TAP Valid Delay Timing.............................................................................................................. 43
ITPCLKOUT Valid Delay Timing.................................................................................................44
Stop Grant/Sleep/Deep Sleep Timing......................................................................................... 44
BCLK Signal Integrity Waveform ................................................................................................ 46
Low-to-High FSB Receiver Ringback Tolerance ........................................................................ 47
High-to-Low FSB Receiver Ringback Tolerance ........................................................................ 47
Low-to-High FSB Receiver Ringback Tolerance for PWRGOOD and TAP Buffers ................... 48
High-to-Low FSB Receiver Ringback Tolerance for PWRGOOD and TAP Buffers ................... 48
Maximum Acceptable Overshoot/Undershoot Waveform........................................................... 53
Micro-FCPGA Package Top and Bottom Isometric Views.......................................................... 55
Micro-FCPGA Package - Top and Side Views ........................................................................... 56
Micro-FCPGA Package - Bottom View ....................................................................................... 58
The Coordinates of the Processor Pins as Viewed from the Top of the Package ...................... 59
Clock Control States ................................................................................................................... 88
Datasheet
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