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Intel

®

82562V 10/100 Mbps

Platform LAN Connect

Datasheet

Product Features

n

IEEE 802.3 10BASE-T/100BASE-TX

compliant physical layer interface

IEEE 802.3u Auto-Negotiation support

Digital Adaptive Equalization control

Link status interrupt capability

XOR tree mode support

3-port LED support (speed, link and

activity)

10BASE-T auto-polarity correction

LAN Connect Interface

PHY detects polarity, MDI-X, and cable

lengths. Auto MDI, MDIX crossover at all

speeds

n

Diagnostic loopback mode

1:1 transmit transformer ratio support

Low power (less than 300 mW in active

transmit mode)

Reduced power in “unplugged mode” (less

than 50 mW)

Automatic detection of “unplugged mode”

3.3 V device

81-pin Mold Cap package--10mm x 10mm

x 1.745mm; 0.635mm Ball, 1.0mm Pitch

Additional Features

n

The 82562V PLC supports strapping options that enable the following operating modes:

— LED support for three logic configurations.

— LAN disable function using one pin.

— Increased transmit strength.

The receive BER performance increases the margin for cable length.

Return Loss performance is improved.

Revision 1.00

January 2006

317757-001

Revision History

Revision

0.25

0.50

1.00

Revision Date

July 2005

October 2005

January 2006

Initial release.

Added correct package information and added more pin names and numbers

Updated the power values and the signal names list

Description

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property

rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel

disclaims any express or implied warranty, relating to sale and/or use of Intel® products including liability or warranties relating to fitness for a particular purpose,

merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life

sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition

and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 82562V PLC may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized

errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by

visiting Intel's website at http://www.intel.com.

Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

* Other brands and names are the property of their respective owners.

Datasheet

Networking Silicon — 82562V

1.0

Introduction

This document is applicable to the Intel

®

82562V 10/100 Mbps Platform LAN Connect device.

1.1

Overview

The Intel

®

82562V 10/100 Mbps Platform LAN Connect is a highly-integrated device designed for

10 or 100 Mbps Ethernet systems. It is based on the IEEE 10BASE-T and 100BASE-TX standards.

The IEEE 802.3u standard for 100BASE-TX defines networking over two pairs of Category 5

unshielded twisted pair cable or Type 1 shielded twisted pair cable.

The 82562V complies with the IEEE 802.3u Auto-Negotiation standard and the IEEE 802.3x Full

Duplex Flow Control standard. The 82562V also includes a PHY interface compliant to the current

platform LAN connect interface.

1.2

References

•

IEEE 802.3 Standard for Local and Metropolitan Area Networks, Institute of Electrical and

Electronics Engineers.

•

82562ET(EM) and 82562V(G) LAN on Motherboard Design Guide. Intel Corporation.

•

Intel

®

I/O Controller Hub 6 (ICH6) Family External Design Specification (EDS), Volume 1,

Revision 1.5V1. Intel Corporation.

•

Intel

®

I/O Controller Hub 6 (ICH6) Family External Design Specification (EDS), Volume 2,

Revision 1.5V2. Intel Corporation.

•

LAN Connect Interface Specification. Intel Corporation.

•

I/O Control Hub 2, 3, and 4 EEPROM Map and Programming Information. Intel Corporation.

•

I/O Control Hub 5, 6, and 7 EEPROM Map and Programming Information. Intel Corporation.

Programming information can be obtained through your local Intel representatives.

1.3

Product Codes

The product ordering code for the 82562V is: EP82562V.

The product ordering code for the 82562V lead-free version is: LU82562V.

Datasheet

1

82562V — Networking Silicon

2.0

82562V Architectural Overview

The 82562V PLC is a 3.3 V device in a 81-pin Mold Cap package. In normal operating mode, the

82562V incorporates all active circuitry required to interface with the Intel

®

ICHx device with an

integrated 10/100 Mbps LAN controller. The 82562V supports a direct interface to all Media

Access Control (MAC) components that meet the Platform LAN connect interface specification.

Figure 1

shows a block diagram of the 82562V architecture.

Digital

Equalizer

Adaptation

Equalizer &

BLW correction

MDI/MDI-X

CRS/Link 10

Detection

Transmit DAC

10/100

Auto-

Negotiation

Bias & Band-

Gap Voltage

Circuit

Clock

Generator

Control

Registers

Digital Clock

Recovery (100)

Digital Clock

Recovery (10)

100Base-TX

PCS

JRSTSYNC

Port LED

Drivers

LILED#

ACTLED#

SPDLED#

RDN/RDP

10Base-T

PCS

LAN

Connect

Interface

3

JTXD[2:0]

JRXD[2:0]

JCLK

TDN/TDP

X1

Crystal

25 MHz

X2

Figure 1. 82562V PLC Block Diagram

2.1

LAN Connect Interface

The 82562V supports a LAN Connect Interface (LCI) as specified in the LCI Specification. The

LAN Connect is the I/O Control Hub 2 (ICH2) interface to the 82562V. The LCI uses an 8-pin

interface, which reduces the pin count from 15, for an Media Independent Interface (MII) PHY. In

addition, its signaling protocol provides greater functionality, such as dynamic power reduction,

from a PLC in comparison to a standard MII PHY.

Figure 2

shows how the 82562V can be used in a 10/100 Mbps ICHx design.

I/O

Control Hub 4

I/O

Control Hub

LAN Controller

(ICH4) LAN

Controller

82562EZ

(Platform LAN

82562V PLC

Connect

Device)

Transmit Differential Pair

(TDP/TDN)

Receive Differential Pair

(RDP/RDN)

Magnetics

System Bus Interface

2

Datasheet

Networking Silicon — 82562V

Figure 2. 82562V PLC 10/100 Mbps Ethernet Solution

2.1.1

Reset/Synchronize Operations

The Reset/Synchronize signal used by the LAN Connect Interface is driven by the ICHx integrated

LAN device. It has two functions:

•

Synchronize. When this pin is activated synchronously for only one LAN connect clock, it is

used for synchronization between the ICHx integrated LAN and PHY on LAN connect word

boundaries.

•

Reset. When this pin is asserted beyond one LAN connect clock, the 82562V uses this signal

as a reset signal. To ensure a reset of the 82562V, the reset should remain active for at least 500

µs.

2.1.2

Reset Considerations

When the 82562V Reset signal (JRSTSYNC) is asserted for at least 500 µs, all internal circuits are

reset. The 82562V can also be reset by setting the MII register Reset bit equal to 1 (Register 0, bit

15).

The 82562V filters out JRSTSYNC pulses with a width of less than 200 ns to distinguish between

a reset and synchronize pulse. Again, the Reset signal should be longer than 500 µs to reset the

82562V.

Datasheet

3

82562V

82562V概述

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