82551QM Fast Ethernet
Multifunction PCI/CardBus
Controller
Networking Silicon - 82551QM
Datasheet
Product Features
Enhanced IP Protocol Support
— TCP, UDP, IPv4 Checksum Offload
— Received Checksum Verification
Quality of Service (QoS)
— Multiple Priority Transmit Queues
Optimum Integration for Lowest Cost Solution
— Integrated IEEE 802.3 10BASE-T and
100BASE-TX compatible PHY
— 32-bit PCI/CardBus master interface
— Modem interface for combination solutions
— Integrated power management functions
— Thin BGA 15mm
2
package
PHY detects polarity, MDI-X, and cable lengths.
Auto MDI/MDI-X crossover at all speeds
XOR tree mode support
Wired for Reduced Total Cost of Ownership
(TCO)
— Wired for Management support
— Integrated Alert Standard Format
— ACPI and PCI Power Management standards
compliance
— Wake on “interesting” packets and link status
change support
— Magic Packet* support
— Remote power up support
High Performance Networking Functions
— Early release
— 8255x controller family chained memory
structure
— Improved dynamic transmit chaining with
multiple priorities transmit queues
— Full pin compatibility with the 82559 and
82550 controllers
— Backward compatible software to the 8255x
controller family (IPSec not supported)
— Full Duplex support at 10 and 100 Mbps
— IEEE 802.3u Auto-Negotiation support
— 3 KB transmit and receive FIFOs
— Fast back-to-back transmission support with
minimum interframe spacing
— IEEE 802.3x 100BASE-TX Flow Control
support
— Adaptive Technology
Low Power Features
— Advanced Power Management capabilities
— Low power 3.3 V device
— Efficient dynamic standby mode
— Deep power down support
— Clock Run protocol support
82551QM Enhancements
— Improved Bit Error Rate performance
— Integrated UNDI ROM support
— HWI support
— Deep power-down state power reduction
Lead-free
1
196-pin Ball Grid Array (BGA).
Devices that are lead-free are marked with a
circled “e1” and have the product code:
LUXXXXX.
1
This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm.
The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on
Hazardous Substances (RoHS)-banned materials, is available at:
ftp://download.intel.com/design/packtech/
material_content_IC_Package.pdf#pagemode=bookmarks
In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the
device. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales
Rerepresentative.
317803-004
Revision 4.0
Revision History
Revision
Date
Oct 2001
Revision
0.6
•
•
•
Description
Removed references to IPSec support and changed description of FLA1/AUXPWR to use a
pull-up resistor if auxiliary power is present, else leave it disconnected.
Changed description of VCCR to show connecting it directly to main 3.3V supply and reduced
text describing bus operations.
Reduced PHY functional description to overview level and reorganized manageability section,
adding ASF text. Added 0Fh as Revision ID and added targeted Icc specs.
Added description for No Connect pins and corrected typographical errors.
Dec 2001
Apr 2002
Mar 2003
Jun 2003
Oct 2003
Mar 2004
Oct 2004
1.0
2.0
2.1
3.0
3.1
3.11
3.2
•
Changed document status to Intel Confidential.
•
•
•
•
•
•
•
•
•
Removed document status and removed references to MDI/MDI-X feature, which is not sup-
ported by the 82551QM
Added information for the 82551IT.
Corrected operating temperature range in specifications to 0° to 70° C.
Added operating temperature reference to Section 1.1
Removed operating temperature reference to Section 1.1.
Added references to MDI/MDI-X feature, which is now supported by the 82551QM and
removed information for the 82551IT.
Updated the section describing “Multiple Priority Transmit Queues”.
Added information about migrating from a 2-layer 0.36 mm wide-trace substrate to a 2-layer
0.32 mm wide-trace substrate. Refer to the section on Package and Pinout Information.
Added statement that no changes to existing soldering processes are needed for the 2-layer
0.32 mm wide-trace substrate change in the section describing “Package Information”.
Added a note for PHY signals RBIAS100 and RBIAS10 to Table 9.
Changed case temperature specification to “0° C to 85° C”.
Added Figure 31 “196 PBGA Package Pad Detail”. The figure shows solder resist opening and
metal diameter dimensions.
Added Section 15 “Reference Schematics”, updated Section 12.1 (changed Tcase to ambient)
and added ordering information to Section 1.4.
Updated Figures 34 and 35. Added Digital I/O and Crystal Input One (X1) Characteristics
(Tables 70 and 71). Updated Section 5.8.4.
Updated Figure 35: changed TEST pull down resistor value (62 K to 1 K).
Updated Table 9 (X1 and X2 pin descriptions).
Nov 2004
3.3
Jan 2005
Apr 2006
Oct 2006
July 2007
Sept 2007
Mar 2008
3.4
3.5
3.6
3.7
3.8
3.9
•
•
•
•
•
•
•
Nov 2008
4.0
•
Updated Tables 70 and 71 (Digital I/O and crystal input one (X1) characteristics).
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82551QM may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countries 708-
296-9333
Intel
®
is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
Copyright © 2008, Intel Corporation.
* Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owners’ benefit, without
intent to infringe.
ii
Datasheet
Networking Silicon — 82551QM
Contents
1.0
Introduction......................................................................................................................... 1
1.1
1.2
1.3
1.4
2.0
2.1
2.2
2.3
2.4
2.5
3.0
3.1
3.2
3.3
3.4
4.0
4.1
4.2
Overview ............................................................................................................... 1
Byte Ordering ........................................................................................................ 1
References ............................................................................................................ 1
Product Ordering Codes........................................................................................ 2
Parallel Subsystem Overview................................................................................ 3
FIFO Subsystem Overview ................................................................................... 4
Manageability Subsystem Overview ..................................................................... 4
10/100 Mbps Serial CSMA/CD Unit Overview ......................................................4
10/100 Mbps Physical Layer Unit.......................................................................... 4
Multiple Priority Transmit Queues ......................................................................... 5
Early Release ........................................................................................................ 5
Hardware Integrity Support ................................................................................... 6
Management Data Interface MDI/MDI-X Feature.................................................. 6
Signal Type Definitions ......................................................................................... 7
PCI Bus and CardBus Interface Signals ............................................................... 8
4.2.1 Address and Data Signals ....................................................................... 8
4.2.2 Interface Control Signals ......................................................................... 8
4.2.3 System and Power Management Signals ............................................... 9
Local Memory Interface Signals .......................................................................... 10
System Management Bus (SMB) Interface Signals ........................................... 12
Test Port Signals ................................................................................................ 13
PHY Signals ....................................................................................................... 13
Power and Ground Signals ................................................................................. 14
Device Initialization..............................................................................................15
5.1.1 Initialization Effects................................................................................. 15
5.1.2 Initialization Effects on TCO Functionality.............................................. 16
PCI and CardBus Interface ................................................................................. 16
5.2.1 Bus Operations....................................................................................... 16
5.2.2 Clock Run Signal.................................................................................... 25
5.2.3 Power Management Event and Card Status Change Signals................ 25
PCI Power Management ..................................................................................... 26
5.3.1 Power States .......................................................................................... 26
5.3.2 Wake-up Events ..................................................................................... 30
CardBus Power Management ............................................................................. 31
Wake on LAN (Preboot Wake-up)....................................................................... 31
Parallel Flash/Modem Interface........................................................................... 32
Serial EEPROM Interface.................................................................................... 33
10/100 Mbps CSMA/CD Unit............................................................................... 35
Architectural Overview ....................................................................................................... 3
Performance Enhancements.............................................................................................. 5
Signal Descriptions.............................................................................................................7
4.3
4.4
4.5
4.6
4.7
5.0
5.1
Media Access Control Functional Description.................................................................. 15
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Datasheet
iii
82551QM — Networking Silicon
5.9
6.0
6.1
5.8.1 Full Duplex ............................................................................................. 35
5.8.2 Flow Control ........................................................................................... 36
5.8.3 Address Filtering Modifications .............................................................. 36
5.8.4 VLAN Support ........................................................................................ 36
Media Independent Interface (MII) Management Interface ................................. 36
100BASE-TX PHY Unit ....................................................................................... 37
6.1.1 100BASE-TX Transmit Clock Generation .............................................. 37
6.1.2 100BASE-TX Transmit Blocks ............................................................... 37
6.1.3 100BASE-TX Receive Blocks ................................................................ 37
6.1.4 100BASE-TX Link Integrity Auto-Negotiation......................................... 38
10BASE-T PHY Functions .................................................................................. 38
6.2.1 10BASE-T Transmit Clock Generation................................................... 38
6.2.2 10BASE-T Transmit Blocks.................................................................... 38
6.2.3 10BASE-T Receive Blocks..................................................................... 38
6.2.4 10BASE-T Link Integrity and Full Duplex ............................................... 39
Auto-Negotiation ................................................................................................. 39
6.3.1 Description ............................................................................................. 39
6.3.2 Parallel Detect and Auto-Negotiation ..................................................... 39
LED Description .................................................................................................. 40
PCI Address Mapping to the Modem .................................................................. 43
Modem Read and Write Cycles .......................................................................... 43
Modem and Preboot eXtension Environment Coexistence................................. 43
7.3.1 Programming Details.............................................................................. 44
7.3.2 Support Circuitry .................................................................................... 44
Alert Standard Format......................................................................................... 45
Heartbeat ............................................................................................................ 46
Ping/Pong............................................................................................................ 46
Watchdog ............................................................................................................ 47
Advanced Power Management Modes ............................................................... 47
Polling ................................................................................................................. 47
Link Loss ............................................................................................................. 47
Acknowledge ....................................................................................................... 47
Function 0: LAN (Ethernet) PCI Configuration Space ......................................... 49
9.1.1 PCI Vendor ID and Device ID Registers ................................................ 49
9.1.2 PCI Command Register ......................................................................... 50
9.1.3 PCI Status Register................................................................................ 51
9.1.4 PCI Revision ID Register........................................................................ 52
9.1.5 PCI Class Code Register ....................................................................... 52
9.1.6 PCI Cache Line Size Register................................................................ 53
9.1.7 PCI Latency Timer ................................................................................. 53
9.1.8 PCI Header Type ................................................................................... 53
9.1.9 PCI Base Address Registers.................................................................. 53
9.1.10 Base Address Registry Summary .......................................................... 56
Physical Layer Functional Description ............................................................................. 37
6.2
6.3
6.4
7.0
7.1
7.2
7.3
Modem Functionality ........................................................................................................ 43
8.0
Manageability Functionality.............................................................................................. 45
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
9.0
Configuration Registers.................................................................................................... 49
9.1
iv
Datasheet
Networking Silicon — 82551QM
9.2
9.1.11 CardBus Card Information Structure (CIS) Pointer ................................ 56
9.1.12 PCI Subsystem Vendor ID and Subsystem ID Registers.......................56
9.1.13 Capability Pointer ................................................................................... 57
9.1.14 Interrupt Line Register............................................................................ 57
9.1.15 Interrupt Pin Register ............................................................................. 57
9.1.16 Minimum Grant Register ........................................................................ 58
9.1.17 Maximum Latency Register.................................................................... 58
9.1.18 Capability ID Register............................................................................. 58
9.1.19 Next Item Pointer.................................................................................... 58
9.1.20 Power Management Capabilities Register ............................................. 58
9.1.21 Power Management Control/Status Register (PMCSR)......................... 59
9.1.22 Data Register ......................................................................................... 60
Function 1: Modem PCI Configuration Space ..................................................... 60
9.2.1 Modem Configuration ID Register .......................................................... 61
9.2.2 Modem Command Register ................................................................... 61
9.2.3 Modem Status Register.......................................................................... 62
9.2.4 Modem Revision ID Register.................................................................. 62
9.2.5 Modem Header Type Register ............................................................... 62
9.2.6 Modem I/O Base Address Register........................................................ 62
9.2.7 Modem Memory Base Address Register................................................ 63
9.2.8 Modem CardBus CIS Pointer .................................................................63
9.2.9 Modem Subsystem Vendor ID Register ................................................. 63
9.2.10 Modem Subsystem ID Register.............................................................. 63
9.2.11 Modem Capabilities Pointer ................................................................... 63
9.2.12 Modem Interrupt Register....................................................................... 63
9.2.13 Modem Power Management Capabilities Register ................................ 63
9.2.14 Modem Power Management Control/Status Register ............................ 64
9.2.15 Modem Data Register ............................................................................ 64
9.2.16 Modem Support in PCI Mode .................................................................64
LAN (Ethernet) Control/Status Registers ............................................................ 65
10.1.1 System Control Block Status Word ........................................................ 66
10.1.2 System Control Block Command Word.................................................. 67
10.1.3 System Control Block General Pointer................................................... 67
10.1.4 PORT ..................................................................................................... 67
10.1.5 Flash Control Register............................................................................ 67
10.1.6 EEPROM Control Register..................................................................... 68
10.1.7 Management Data Interface Control Register........................................ 68
10.1.8 Receive Direct Memory Access Byte Count........................................... 68
10.1.9 Flow Control Register............................................................................. 68
10.1.10 Power Management Driver Register ...................................................... 69
10.1.11 General Control Register........................................................................ 70
10.1.12 General Status Register ......................................................................... 70
10.1.13 Ethernet Card Status Change Registers ................................................ 70
Statistical Counters ............................................................................................. 73
Modem Control/Status Registers ........................................................................ 75
10.3.1 Modem Base Memory Addressing ......................................................... 76
10.3.2 Modem Base I/O Addressing .................................................................76
10.3.3 Modem CardBus CSTCHG Registers ....................................................76
10.0
Control/Status Registers .................................................................................................. 65
10.1
10.2
10.3
Datasheet
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