DATASHEET
X9315
Low Noise, Low Power, 32 Taps Digitally Controlled Potentiometer
(XDCP™)
The Intersil X9315 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a 3-wire interface.
The potentiometer is implemented by a resistor array
composed of 31 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS, U/D, and INC inputs.
The position of the wiper can be stored in nonvolatile
memory and then be recalled upon a subsequent power-up
operation.
The device can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including:
• Control
• Parameter Adjustments
• Signal Processing
FN8179
Rev.2.00
December 21, 2009
Features
• Solid-state potentiometer
• 3-wire serial interface
• 32 wiper tap points
- Wiper position stored in nonvolatile memory and
recalled on power-up
• 31 resistive elements
- Temperature compensated
- End to end resistance range ± 20%
- Terminal voltage, 0 to V
CC
• Low power CMOS
- V
CC
= 2.7V or 5V
- Active current, 80/400µA max.
- Standby current, 5µA max.
• High reliability
- Endurance, 100,000 data changes per bit
- Register data retention, 100 years
• R
TOTAL
values = 10k, 50k, 100k
• Packages
- 8 Ld SOIC, MSOP and PDIP
• Pb-free available (RoHS compliant)
Block Diagram
U/D
INC
CS
R
H
/V
H
Control
and
Memory
R
W
/V
W
R
L
/V
L
Store and
Recall
Control
Circuitry
5-Bit
Nonvolatile
Memory
5-Bit
Up/Down
Counter
31
30
29
28
One
of
Thirty
Two
Decoder
2
V
SS
(Ground)
General
V
CC
V
SS
1
0
R
L
/V
L
R
W
/V
W
Detailed
R
H
/V
H
V
CC
(Supply Voltage)
Up/Down
(U/D)
Increment
(INC)
Device Select
(CS)
Transfer
Gates
Resistor
Array
FN8179 Rev.2.00
December 21, 2009
Page 1 of 16
X9315
Ordering Information
PART NUMBER
X9315WMZ (Note 2)
X9315WMZT1 (Notes 1, 2)
X9315WMIT2 (Note 1)
X9315WMIZ (Note 2)
X9315WMIZT1 (Notes 1, 2)
X9315WP
X9315WST1 (Note 1)
X9315WSZ (Note 2)
X9315WSZT1 (Notes 1, 2)
X9315WSI
X9315WSIT1 (Note 1)
X9315WSIZ (Note 2)
X9315WSIZT1 (Notes 1, 2)
X9315UMZ (Note 2)
X9315UMZT1 (Notes 1, 2)
X9315UMI
X9315UMIT1 (Notes 1, 2)
X9315UMIZ (Note 2)
X9315UMIZT1 (Notes 1, 2)
X9315UST2 (Note 1)
X9315USZ (Note 2)
X9315USZT1 (Notes 1, 2)
X9315USIZ (Note 2)
X9315USIZT1 (Notes 1, 2)
X9315TMZ (Note 2)
X9315TMZT1 (Notes 1, 2)
X9315TMIZ (Note 2)
X9315TMIZT1 (Notes 1, 2)
X9315TSZ (Note 2)
X9315TSZT1 (Notes 1, 2)
X9315TSIZ (Note 2)
X9315TSIZT1 (Notes 1, 2)
X9315WMZ-2.7 (Note 2)
X9315WMZ-2.7T1 (Notes 1, 2)
X9315WMI-2.7T2 (Note 1)
X9315WMIZ-2.7 (Note 2)
X9315WMIZ-2.7T1 (Notes 1, 2)
X9315WS-2.7
PART MARKING
DDT
DDT
AAX
AKW
AKW
X9315WP
X9315W
X9315W Z
X9315W Z
X9315W I
X9315W I
X9315W ZI
X9315W ZI
DDS
DDS
AEB
AEB
DDR
DDR
X9315U
X9315U Z
X9315U Z
X9315U ZI
X9315U ZI
DDN
DDN
DDL
DDL
X9315T Z
X9315T Z
X9315T ZI
X9315T ZI
AOI
AOI
AAV
AKX
AKX
X9315W F
2.7 to 5.5
10
100
50
V
CC
LIMITS
(V)
5 ±10%
R
TOTAL
(k)
10
TEMP RANGE
(°C)
0 to 70
0 to 70
-40 to 85
-40 to 85
-40 to 85
0 to 70
0 to 70
0 to 70
0 to 70
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
-40 to 85
0 to 70
PACKAGE
PKG.
DWG. #
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP
M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld PDIP
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
MDP0031
M8.15E
M8.15
M8.15
M8.15E
M8.15E
M8.15
M8.15
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP
8 Ld MSOP
M8.118
M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
M8.15E
M8.15
M8.15
M8.15
M8.15
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
M8.15
M8.15
M8.15
M8.15
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP
M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld SOIC
M8.15E
FN8179 Rev.2.00
December 21, 2009
Page 2 of 16
X9315
Ordering Information
(Continued)
PART NUMBER
X9315WS-2.7T1 (Note 1)
X9315WSZ-2.7 (Note 2)
X9315WSZ-2.7T1 (Notes 1, 2)
X9315WSI-2.7T1 (Note 1)
X9315WSIZ-2.7 (Note 2)
X9315WSIZ-2.7T1 (Notes 1, 2)
X9315UMZ-2.7 (Note 2)
X9315UMZ-2.7T1 (Notes 1, 2)
X9315UMIZ-2.7 (Note 2)
X9315UMIZ-2.7T1 (Notes 1, 2)
X9315US-2.7T2 (Note 1)
X9315USZ-2.7 (Note 2)
X9315USZ-2.7T1 (Notes 1, 2)
X9315USI-2.7
X9315USIZ-2.7 (Note 2)
X9315USIZ-2.7T1 (Notes 1, 2)
X9315TMZ-2.7 (Note 2)
X9315TMZ-2.7T1 (Notes 1, 2)
X9315TMI-2.7T1 (Note 1)
X9315TMIZ-2.7 (Note 2)
X9315TMIZ-2.7T1 (Notes 1, 2)
X9315TSZ-2.7 (Note 2)
X9315TSZ-2.7T1 (Notes 1, 2)
X9315TSIZ-2.7 (Note 2)
X9315TSIZ-2.7T1 (Notes 1, 2)
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
PART MARKING
X9315W F
X9315W ZF
X9315W ZF
X9315W G
X9315W ZG
X9315W ZG
AKU
AKU
AJG
AJG
X9315U F
X9315U ZF
X9315U ZF
X9315U G
X9315U ZG
X9315U ZG
DDP
DDP
ADY
DDM
DDM
X9315T ZF
X9315T ZF
X9315T ZG
X9315T ZG
100
50
V
CC
LIMITS
(V)
2.7 to 5.5
R
TOTAL
(k)
10
TEMP RANGE
(°C)
0 to 70
0 to 70
0 to 70
-40 to 85
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
0 to 70
-40 to 85
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
PACKAGE
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
PKG.
DWG. #
M8.15E
M8.15
M8.15
M8.15E
M8.15
M8.15
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
M8.15E
M8.15
M8.15
M8.15E
M8.15
M8.15
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP
M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
M8.15
M8.15
M8.15
M8.15
FN8179 Rev.2.00
December 21, 2009
Page 3 of 16
X9315
Pin Configuration
X9315
(8 LD MSOP, SOIC, PDIP)
TOP VIEW
INC
U/D
R
H
/V
H
V
SS
1
2
3
4
X9315
8
7
6
5
V
CC
CS
R
L
/V
L
R
W
/V
W
operation is complete the X9315 will be placed in the low
power standby mode until the device is selected once again.
Principles of Operation
There are three sections of the X9315: the input control,
counter and decode section; the nonvolatile memory; and the
resistor array. The input control section operates just like an
up/down counter. The output of this counter is decoded to turn
on a single electronic switch connecting a point on the resistor
array to the wiper output. Under the proper conditions the
contents of the counter can be stored in nonvolatile memory
and retained for future use. The resistor array is comprised of
31 individual resistors connected in series. At either end of the
array and between each resistor is an electronic switch that
transfers the connection at that point to the wiper.
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions. If
the wiper is moved several positions, multiple taps are
connected to the wiper for t
IW
(INC to V
W
change). The
R
TOTAL
value for the device can temporarily be reduced by a
significant amount if the wiper is moved several positions.
When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled and
the wiper is set to the value last stored.
Pin Names
SYMBOL
RH/VH
RW/VW
RL/VL
VSS
VCC
U/D
INC
CS
DESCRIPTION
High terminal
Wiper terminal
Low terminal
Ground
Supply voltage
Up/Down control input
Increment control input
Chip Select control input
Pin Description
R
H
/V
H
and R
L
/V
L
The high (R
H
/V
H
) and low (R
L
/V
L
) terminals of the X9315 are
equivalent to the fixed terminals of a mechanical
potentiometer. The minimum voltage is V
SS
and the maximum
is V
CC
. The terminology of R
L
/V
L
and R
H
/V
H
references the
relative position of the terminal in relation to wiper movement
direction selected by the U/D input, and not the voltage
potential on the terminal.
Instructions and Programming
The INC, U/D and CS inputs control the movement of the wiper
along the resistor array. With CS set LOW the device is
selected and enabled to respond to the U/D and INC inputs.
HIGH to LOW transitions on INC will increment or decrement
(depending on the state of the U/D input) a five bit counter. The
output of this counter is decoded to select one of thirty two
wiper positions along the resistive array.
The value of the counter is stored in nonvolatile memory
whenever CS transitions HIGH while the INC input is also
HIGH.
The system may select the X9315, move the wiper and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as described above and once the new position is
reached, the system must keep INC LOW while taking CS
HIGH. The new wiper position will be maintained until changed
by the system or until a power-up/down cycle recalled the
previously stored data.
This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during system
operation minor adjustments could be made. The adjustments
R
W
/V
W
R
W
/V
w
is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the control inputs. The
wiper terminal series resistance is typically 200 at V
CC
= 5V.
Up/Down (U/D)
The U/D input controls the direction of the wiper movement
and whether the counter is incremented or decremented.
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the counter
in the direction indicated by the logic level on the U/D input.
Chip Select (CS)
The device is selected when the CS input is LOW. The current
counter value is stored in nonvolatile memory when CS is
returned HIGH while the INC input is also HIGH. After the store
FN8179 Rev.2.00
December 21, 2009
Page 4 of 16
X9315
might be based on user preference, system parameter
changes due to temperature drift, etc...
The state of U/D may be changed while CS remains LOW. This
allows the host system to enable the device and then move the
wiper up and down until the proper trim is attained.
Power-up and Down Requirements
There are no restrictions on the power-up or power-down
conditions of V
CC
and the voltages applied to the
potentiometer pins provided that V
CC
is always more positive
than or equal to V
H
, V
L
, and V
W
, i.e., V
CC
V
H
, V
L
, V
W
. The
V
CC
ramp rate spec is always in effect.
Mode Selection
CS
L
L
H
H
X
L
L
L
INC
U/D
H
L
X
X
X
H
L
Wiper up
Wiper down
Store wiper position to nonvolatile
memory
Standby
No store, return to standby
Wiper Up (not recommended)
Wiper Down (not recommended)
MODE
FN8179 Rev.2.00
December 21, 2009
Page 5 of 16
电子竞赛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
