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CY7C4421/4201/4211/4221 CY7C4231/4241/425164/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Features
• High-speed, low-power, First-In, First-Out (FIFO)
memories
— 64 × 9 (CY7C4421)
— 256 × 9 (CY7C4201)
— 512 × 9 (CY7C4211)
— 1K × 9 (CY7C4221)
— 2K × 9 (CY7C4231)
— 4K × 9 (CY7C4241)
— 8K × 9 (CY7C4251)
• High-speed 100-MHz operation (10 ns Read/Write cycle
time)
• Low power (I
CC
= 35 mA)
• Fully asynchronous and simultaneous Read and Write
operation
• Empty, Full, and Programmable Almost Empty and
Almost Full status flags
• TTL-compatible
• Expandable in width
• Output Enable (OE) pin
• Independent Read and Write enable pins
• Center power and ground pins for reduced noise
• Width-expansion capability
• Space saving 7 mm × 7 mm 32-pin TQFP
•
Pin-compatible and functionally equivalent to
IDT72421, 72201, 72211, 72221, 72231, and 72241
• Pb-Free Packages Available
Functional Description
The CY7C42X1 are high-speed, low-power FIFO memories
with clocked Read and Write interfaces. All are 9 bits wide. The
CY7C42X1 are pin-compatible to IDT722X1. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor inter-
faces, and communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
Write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running Read clock (RCLK) and two
Read-enable pins (REN1, REN2). In addition, the CY7C42X1
has an output enable pin (OE). The Read (RCLK) and Write
(WCLK) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
Read/Write applications. Clock frequencies up to 100 MHz are
achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data.
Logic Block Diagram
D0 - 8
Pin Configurations
PLCC
Top View
4 3 2 1 32 3130
29
5
28
6
27
7
26
8
9
25
10
24
11
23
12
22
21
13
141516 171819 20
WCLK WEN1 WEN2/LD
FLAG
PROGRAM
REGISTER
Write
CONTROL
FLAG
LOGIC
Dual Port
RAM Array
64 x 9
Write
POINTER
8k x 9
Read
POINTER
EF
PAE
PAF
FF
D
1
D
0
PAF
PAE
GND
REN1
RCLK
REN2
OE
D
2
D
3
D
4
D
5
D
6
D
7
D
8
RS
WEN1
WCLK
WEN2/LD
V
CC
Q
8
Q
7
Q
6
Q
5
INPUT
REGISTER
D
3
EF
D
4
FF
Q
D
5 0
Q
1
D
6
Q
2
D
7
Q
3
D
8
Q
4
RS
TQFP
Top View
24
23
22
21
20
19
18
17
WEN1
WCLK
WEN2/LD
V
CC
Q
8
Q
7
Q
6
Q
5
D
1
D
0
PAF
PAE
GND
REN1
RCLK
REN2
RS
RESET
LOGIC
THREE-ST
ATE
OUTPUT REGISTER
OE
Q0 - 8
Read
CONTROL
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
D
2
32 31 30 29 28 27 26 25
FF
Q
0
Q
1
Q
2
RCLK REN1 REN2
Cypress Semiconductor Corporation
Document #: 38-06016 Rev. *C
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised August 2, 2005
OE
EF
Q
3
Q
4
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Selection Guide
-10
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
Active Power Supply Current
Commercial
Industrial
CY7C4421
Density
64 × 9
CY7C4201
256 × 9
CY7C4211
512 × 9
100
8
10
3
0.5
8
35
40
CY7C4221
1K × 9
-15
66.7
10
15
4
1
10
35
40
CY7C4231
2K × 9
-25
40
15
25
6
1
15
35
40
CY7C4241
4K × 9
CY7C4251
8K × 9
Unit
MHz
ns
ns
ns
ns
ns
ICC1
Pin Definitions
Pin
D
0–8
Q
0–8
WEN1
Name
Data Inputs
Data Outputs
Write Enable 1
I/O
I
O
I
Data Inputs for 9-bit Bus
Data Outputs for 9-bit Bus
The only Write enable to have programmable flags when device is configured. Data is
written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH.
If the FIFO is configured to have two Write enables, data is written on a LOW-to-HIGH
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
If HIGH at reset, this pin operates as a second Write enable. If LOW at reset, this pin
operates as a control to Write or Read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into
the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags,
WEN2/LD is held LOW to write or read the programmable flag offsets.
Enables Device for Read Operation
The rising edge clocks data into the FIFO when WEN1 is LOW, WEN2/LD is HIGH, and
the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the
FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable
flag-offset register.
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO.
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO.
Resets device to empty condition. A reset is required before an initial Read or Write
operation after power-up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected.
If OE is HIGH, the FIFO’s outputs are in High-Z (high-impedance) state.
Description
WEN2/LD Dual Write Enable 2
Mode Pin
Load
I
I
REN1, REN2
WCLK
Read Enable
Inputs
Write Clock
I
I
RCLK
Read Clock
I
EF
FF
PAE
PAF
RS
OE
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Reset
Output Enable
O
O
O
O
I
I
Document #: 38-06016 Rev. *C
Page 2 of 19
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Functional Description
The CY7C42X1 provides four status pins: Empty, Full, Almost
Empty, Almost Full. The Almost Empty/Almost Full flags are
programmable to single word granularity. The programmable
flags default to Empty – 7 and Full – 7.
The flags are synchronous, i.e., they change state relative to
either the Read clock (RCLK) or the Write clock (WCLK).
When entering or exiting the Empty and Almost Empty states,
the flags are updated exclusively by the RCLK. The flags
denoting Almost Full, and Full states are updated exclusively
by WCLK. The synchronous flag architecture guarantees that
the flags maintain their status for at least one cycle.
All configurations are fabricated using advanced 0.65µ N-Well
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
maintains the data of the last valid Read on its Q
0–8
outputs
even after additional reads occur.
Write Enable 1 (WEN1).
If the FIFO is configured for program-
mable flags, Write Enable 1 (WEN1) is the only Write enable
control pin. In this configuration, when Write Enable 1 (WEN1)
is LOW, data can be loaded into the input register and RAM
array on the LOW-to-HIGH transition of every Write clock
(WCLK). Data is stored is the RAM array sequentially and
independently of any on-going Read operation.
Write Enable 2/Load (WEN2/LD).
This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags
or to have two Write enables, which allows for depth
expansion. If Write Enable 2/Load (WEN2/LD) is set active
HIGH at Reset (RS = LOW), this pin operates as a second
Write enable pin.
If the FIFO is configured to have two Write enables, when
Write Enable (WEN1) is LOW and Write Enable 2/Load
(WEN2/LD) is HIGH, data can be loaded into the input register
and RAM array on the LOW-to-HIGH transition of every Write
clock (WCLK). Data is stored in the RAM array sequentially
and independently of any on-going Read operation.
Architecture
The CY7C42X1 consists of an array of 64 to 8K words of 9 bits
each (implemented by a dual-port array of SRAM cells), a
Read pointer, a Write pointer, control signals (RCLK, WCLK,
REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF).
Programming
When WEN2/LD is held LOW during Reset, this pin is the load
(LD) enable for flag offset programming. In this configuration,
WEN2/LD can be used to access the four 8-bit offset registers
contained in the CY7C42X1 for writing or reading data to these
registers.
When the device is configured for programmable flags and
both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH
transition of WCLK writes data from the data inputs to the
empty offset least significant bit (LSB) register. The second,
third, and fourth LOW-to-HIGH transitions of WCLK store data
in the empty offset most significant bit (MSB) register, full
offset LSB register, and full offset MSB register, respectively,
when WEN2/LD and WEN1 are LOW. The fifth LOW-to-HIGH
transition of WCLK while WEN2/LD and WEN1 are LOW
writes data to the empty LSB register again.
Figure 1
shows
the registers sizes and default values for the various device
types.
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal
Read and Write operation. The next time WEN2/LD is brought
LOW, a Write operation stores data in the next offset register
in sequence.
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2
are LOW. LOW-to-HIGH transitions of RCLK Read register
contents to the data outputs. Writes and reads should not be
preformed simultaneously on the offset registers.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition
signified by EF being LOW. All data outputs (Q
0–8
) go LOW
t
RSF
after the rising edge of RS. In order for the FIFO to reset
to its default state, a falling edge must occur on RS and the
user must not read or Write while RS is LOW. All flags are
guaranteed to be valid t
RSF
after RS is taken LOW.
FIFO Operation
When the WEN1 signal is active LOW and WEN2 is active HIGH,
data present on the D
0–8
pins is written into the FIFO on each
rising edge of the WCLK signal. Similarly, when the REN1 and
REN2 signals are active LOW, data in the FIFO memory will
be presented on the Q
0–8
outputs. New data will be presented
on each rising edge of RCLK while REN1 and REN2 are
active. REN1 and REN2 must set up t
ENS
before RCLK for it
to be a valid Read function. WEN1 and WEN2 must occur t
ENS
before WCLK for it to be a valid Write function.
An output enable (OE) pin is provided to three-state the Q
0–8
outputs when OE is asserted. When OE is enabled (LOW),
data in the output register will be available to the Q
0–8
outputs
after t
OE
.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
Document #: 38-06016 Rev. *C
Page 3 of 19
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
64 × 9
8
6 5
0
8
256 × 9
7
Empty Offset (LSB) Reg.
Default Value = 007h
512 × 9
0
8
7
Empty Offset (LSB) Reg.
Default Value = 007h
1K × 9
0
8
7
Empty Offset (LSB) Reg.
Default Value = 007h
0
Empty Offset (LSB) Reg.
Default Value = 007h
8
0
8
0
8
1
(MSB)
0
0
8
1
(MSB)
00
0
8
6 5
Full Offset (LSB) Reg
Default Value = 007h
0
8
7
Full Offset (LSB) Reg
Default Value = 007h
0
8
7
Full Offset (LSB) Reg
Default Value = 007h
0
8
7
Full Offset (LSB) Reg
Default Value = 007h
0
8
0
8
0
8
1
(MSB)
0
0
8
1
(MSB)
00
0
2K × 9
8
7
Empty Offset (LSB) Reg.
Default Value = 007h
4K × 9
0
8
7
Empty Offset (LSB) Reg.
Default Value = 007h
8K × 9
0
8
7
Empty Offset (LSB) Reg.
Default Value = 007h
0
8
2
(MSB)
000
0
8
3
(MSB)
0000
0
8
4
(MSB)
00000
0
8
7
Full Offset (LSB) Reg
Default Value = 007h
0
8
7
Full Offset (LSB) Reg
Default Value = 007h
0
8
7
Full Offset (LSB) Reg
Default Value = 007h
0
8
2
(MSB)
000
0
8
3
(MSB)
0000
0
8
4
(MSB)
00000
0
Figure 1. Offset Register Location and Default Values
Document #: 38-06016 Rev. *C
Page 4 of 19
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