trol, with the use of system clock, I/O transactions are possible
on every clock cycle. Range of operating frequencies, program-
mable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
ORDERING INFORMATION
Part NO.
KM23SV32205T-15
KM23SV32205T-20
KM23SV32205T-30
MAX Freq.
66MHz
50MHz
33MHz
LVTTL
86TSOP2
Interface
Package
FUNCTIONAL BLOCK DIAGRAM
Q0
Q16
.
Output
.
.
Buffer
Q15
Q31
Row Decoder
Sense AMP.
Row Buffer
1M x 32
Cell Array
Address Register
CLK
ADD
Column Decoder
Col. Buffer
LRAS
Latency & Burst Length
LCKE
LRAS
LMR
LCAS
Timing
CLK
CKE
MR
Register
RAS
Programming Register
CAS
CS
DQM
*
Samsung Electronics reserves the right to
change products or specification without notice.
KM23SV32205T
PIN CONFIGURATION (TOP VIEW)
Synch. MROM
V
DD
Q0
V
DD
Q
Q16
Q1
VssQ
Q17
Q2
V
DD
Q
Q18
Q3
VssQ
Q19
MR#
V
DD
DQM
NC
CAS#
RAS#
CS#
WORD#
A12
A11
A10
A0
A1
A2
NC
V
DD
NC
Q4
VssQ
Q20
Q5
V
DD
Q
Q21
Q6
VssQ
Q22
Q7
V
DD
Q
Q23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
Vss
Q31
VssQ
Q15
Q30
V
DD
Q
Q14
Q29
VssQ
Q13
Q28
V
DD
Q
Q12
NC
Vss
NC
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
NC
Vss
NC
Q27
V
DD
Q
Q11
Q26
VssQ
Q10
Q25
V
DD
Q
Q9
Q24
VssQ
Q8
Vss
86TSOPII - 400
(0.5 mm Pin Pitch)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
KM23SV32205T
PIN FUNCTION DESCRIPTION
PIN
CLK
CS
NAME
System Clock
Chip Select
INPUT FUNCTION
Active on the rising edge to sample all inputs.
Synch. MROM
Disables or enables device operation by masking or enabling all inputs except
CLK and CKE.
Masks system clock to freeze operation from the next clock cycle. CKE should be
enabled at least one cycle prior to new command. Disables input buffers for power down
in standby mode.
Row / column addresses are multiplexed on the same pins.
Row address: RA
0
~ RA
12
, column address: CA
0
~ CA
6
(x32): CA
0
~ CA
7
(x16)
Latches row addresses on the rising edge of the CLK with RAS low.
Enables row access
Latches column addresses on the rising edge of the CLK with CAS low.
Enables column access.
Enables mode register set with MR low. (Simultaneously CS,RAS and CAS are low)
CKE
Clock Enable
A
0
~ A
12
RAS
CAS
MR
Q
0
~ Q
31
V
DD
/V
SS
V
DD
Q
/V
SS
Q
WORD
DQM
N.C
Address
Row Address Strobe
Column Address Strobe
Mode Register Set
Data Output
Power Supply/Ground
Data Output Power/
Ground
x32/x16 Mode Selection
Data-out Masking
No Connection
Power and ground for the input buffers and the core logic.
Power and ground for the output buffers.
Double word mode/word mode, depending on polarity of WORD pin.
Should be set before CAS enabling.
It works similar to OE during read operation.
This pin is recommended to be left No Connection on the device.
Note1. V
DD
and V
DD
Q is same voltage.
KM23SV32205T
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on V
DD
Relative to Vss
Voltage on Any Pin Relative to Vss
Operating Temperature
Storage Temperature
Short circuit current
Power Dissipation
Symbol
V
DD
, V
DD
Q
V
IN
, V
OUT
T
A
T
STG
I
OS
P
D
Min
-0.5
-0.5
0
-55
-
-
Max
4.6
Synch. MROM
Unit
V
V
°C
°C
mA
W
V
DD
+ 0.5≤4.6
70
125
50
1
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
DC OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to V
SS
, T
A
=0 to 70°C)
Parameter
Supply Voltage
Supply Voltage(Ground)
Symbol
V
DD
, V
DD
Q
V
SS,
V
SS
Q
Min
3.0
0
Typ
3.3
0
Max
3.6
0
Unit
V
V
DC CHARACTERISTICS
Parameter
Standby Current ( Note3)
Active Standby Current
Burst Mode Operating Current
Input Leakage Current
Output Leakage Current (Dout Disabled)
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level (Logic 1)
Output Low Voltage Level (Logic 0)
Symbol
I
CC3P
I
CC3PS
I
CC3N
I
CC4
I
IL
I
OL
V
IH
V
IL
V
OH
V
OL
Min
-
-
-
-
-10
-10
2.0
-0.3
2.4
-
Max
150
150
50
150
10
10
V
DD
+ 0.3
0.8
-
0.4
Unit
uA
uA
mA
mA
uA
uA
V
V
V
V
Test Condition
CKE≤V
IL
(Max), t
CC
=Min
CKE=0, t
CC
=Min
CS≥V
IH
(Min), t
CC
=Min,
All Outputs Open
t
CC
=Min, All Outputs Open
0V≤V
IN
≤V
DD
+ 0.3V
Pins not under test=0V
(0V≤V
OUT
≤V
DD
Max)
Q# in High-Z
(Note1)
(Note2)
I
OH
=-2mA
I
OL
=2mA
Note : 1. V
IH
(Max)=4.6V for pulse width≤10ns acceptable, pulse width measured at 50% of pulse amplitude.
2. V
IL
(Min)=-1.5V for pulse width≤10ns acceptable, pulse width measured at 50% of pulse amplitude.
3. The condition is the same as Self Refresh Mode of SDRAM, that is, in this case CS,RAS,CAS have to be set to Low, MR has to be set to High.
KM23SV32205T
Parameter
Timing Reference Levels of Input/Output Signals
Input Signal Levels
Transition Time (Rise & Fall) of Input Signals
Output Load
Value
1.4V
Synch. MROM
AC OPERATING TEST CONDITIONS
(T
A
= 0 to 70°C, V
DD
= 3.3V±0.3V, unless otherwise noted.)
V
IH
/V
IL
=2.4V/0.4V
tr/tf=1ns/1ns
LVTTL
Note : If CLK transition time is longer than 1ns, timing parameters should be compensated. Add [(tr+tf)/2-1]ns for transition time longer than 1ns. Transi-
tion time is measured between V
IL
(Max) and V
IH
(Min).
3.3V
Vtt=1.4V
1200Ω
Output
870Ω
50pF
V
OH
(DC)=2.4V, I
OH
=-2mA
V
OL
(DC)=0.4V, I
OL
=2mA
Output
Z
0
=50Ω
50Ω
50pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETERS
(AC operating conditions unless otherwise noted)
Parameter
CLK Cycle Time
CLK to Valid Output Delay
Data Output Hold Time
CLK High Pulse Width
CLK Low Pulse Width
Row-active to Row-active
Input Setup Time
Input Hold Time
CLK to Output in Low-Z
CLK to Output in High-Z
Transition Time
Valid CAS Enable to Valid CAS Enable
Symbol
t
CC
t
SAC
t
OH
t
CH
t
CL
t
RC
t
SS
t
SH
t
SLZ
t
SHZ
t
T
t
VCVC
up to 66MHz
Min
15
-
4
4
4
10
4
2
0
-
0.1
8
Max
-
10
-
-
-
-
-
-
-
10
10
-
up to 50 Mhz
Min
20
-
4
6.5
6.5
9
4
2
0
-
0.1
7
Max
-
10
-
-
-
-
-
-
-
15
10
-
up to 33MHz
Min
30
-
4
11.5
11.5
9
4
2
0
-
0.1
6
Max
-
10
-
-
-
-
-
-
-
25
10
-
ns
ns
ns
ns
ns
clks
ns
ns
ns
ns
ns
clks
2
1
Unit
Notes
Note :
1. These t
RC
values are for BL=8. For BL=4, t
RC
=6 clks for up to 66MHz, t
RC
=5 clks for up to 50MHz, and t
RC
=5 clks for up to 33MHz. RAS latency
increase means, a simultaneous t
RC
increase in the same number of cycles.
( If RAS latency is 3 clks, t
RC
is 12 clks for BL=8.) Refer to attached technical note for gapless operation.
单片机
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