4M
×
4-Bit Dynamic RAM
2k & 4k Refresh
(Hyper Page Mode - EDO)
Advanced Information
• 4 194 304 words by 4-bit organization
• 0 to 70
°C
operating temperature
• Hyper Page Mode - EDO - operation
• Performance:
-50
HYB 5116405BJ-50/-60
HYB 5117405BJ-50/-60
HYB 3116405BJ/BT(L)-50/-60
HYB 3117405BJ/BT-50/-60
-60
60
15
30
25
ns
ns
ns
ns
t
RAC
RAS access time
t
CAC
CAS access time
t
AA
t
RC
Access time from address
Read/Write cycle time
50
13
25
84
20
104 ns
t
HPC
Hyper page mode (EDO) cycle time
• Power dissipation, refresh & addressing:
HYB 5116405 HYB 3116405 HYB 5117405 HYB 3117405
-50
Power supply
Addressing
Refresh
L-version
Active
TTL Standby
CMOS Standby
CMOS Standby
(L-version)
275
11
5.5
–
-60
-50
-60
-50
-60
-50
-60
5 V
±
10%
12/10
3.3 V
±
0.3 V
12/10
5 V
±
10%
11/11
–
440
11
5.5
–
385
288
7.2
3.6
–
252
mW
mW
mW
mW
3.3 V
±
0.3 V
11/11
4096 cylces / 64 ms
4096 cycles / 128 ms
220
180
7.2
3.6
0.72
144
2048 cycles / 32 ms
• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,
test mode and Self Refresh (on L-versions only)
• All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible
• Plastic Package:
P-SOJ-26/24-1
300 mil
P-TSOPII-26/24-1 300 mil
Semiconductor Group
1
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M
×
4 EDO-DRAM
The HYB 5(3)116(7)405 are 16 MBit dynamic RAMs based on die revisions “G” & “F” and organized
as 4 194 304 words by 4-bits. The HYB 5(3)116(7)405BJ/BT(L) utilizes a submicron CMOS silicon
gate process technology, as well as advanced circuit techniques to provide wide operating margins,
both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)116(7)405
to be packaged in a standard SOJ-26/24 and TSOPII-26/24 plastic package with 300 mil width.
These packages provide high system bit densities and are compatible with commonly used
automatic testing and insertion equipment. The HYB 3116(7)405BTL have a very low power “sleep
mode” supported by Self Refresh.
Ordering Information
Type
2k-Refresh Versions:
HYB 5117405BJ-50
HYB 5117405BJ-60
HYB 3117405BJ-50
HYB 3117405BJ-60
HYB 3117405BT-50
HYB 3117405BT-60
4k-Refresh Versions:
HYB 5116405BJ-50
HYB 5116405BJ-60
HYB 3116405BJ-50
HYB 3116405BJ-60
HYB 3116405BT-50
HYB 3116405BT-60
Q67100-Q1098 P-SOJ-26/24-1 300 mil
Q67100-Q1099 P-SOJ-26/24-1 300 mil
on request
on request
on request
on request
P-SOJ-26/24-1 300 mil
P-SOJ-26/24-1 300 mil
5 V 50 ns EDO-DRAM
5 V 60 ns EDO-DRAM
3.3 V 50 ns EDO-DRAM
3.3 V 60 ns EDO-DRAM
Q67100-Q1101 P-SOJ-26/24-1 300 mil
Q67100-Q1102 P-SOJ-26/24-1 300 mil
on request
on request
on request
on request
P-SOJ-26/24-1 300 mil
P-SOJ-26/24-1 300 mil
5 V 50 ns EDO-DRAM
5 V 60 ns EDO-DRAM
3.3 V 50 ns EDO-DRAM
3.3 V 60 ns EDO-DRAM
Ordering Code Package
Descriptions
P-TSOPII-26/24-1 300 mil 3.3 V 50 ns EDO-DRAM
P-TSOPII-26/24-1 300 mil 3.3 V 60 ns EDO-DRAM
P-TSOPII-26/24-1 300 mil 3.3 V 50 ns EDO-DRAM
P-TSOPII-26/24-1 300 mil 3.3 V 60 ns EDO-DRAM
P-TSOPII-26/24-1 300 mil 3.3 V 50 ns LP-EDO-DRAM
P-TSOPII-26/24-1 300 mil 3.3 V 60 ns LP-EDO-DRAM
HYB 3116405BTL-50 on request
HYB 3116405BTL-60 on request
Semiconductor Group
2
1998-10-01
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