Datasheet> 器件分类 > 存储> 存储> HYS72D64020GR-7-X

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HYS72D64020GR-7-X: 产品描述DDR DRAM Module, 64MX72, 0.75ns, CMOS, DIMM-184; 产品类别存储存储; 文件大小278KB，共23页; 制造商Infineon(英飞凌); 官网地址http://www.infineon.com/

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HYS72D64020GR-7-X概述

DDR DRAM Module, 64MX72, 0.75ns, CMOS, DIMM-184

HYS72D64020GR-7-X规格参数

参数名称	属性值
厂商名称	Infineon(英飞凌)
零件包装代码	DIMM
包装说明	,
针数	184
Reach Compliance Code	unknown
ECCN代码	EAR99
访问模式	DUAL BANK PAGE BURST
最长访问时间	0.75 ns
其他特性	AUTO/SELF REFRESH
JESD-30 代码	R-XDMA-N184
内存密度	4831838208 bit
内存集成电路类型	DDR DRAM MODULE
内存宽度	72
功能数量	1
端口数量	1
端子数量	184
字数	67108864 words
字数代码	64000000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	64MX72
封装主体材料	UNSPECIFIED
封装形状	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY
认证状态	Not Qualified
自我刷新	YES
最大供电电压 (Vsup)	2.7 V
最小供电电压 (Vsup)	2.3 V
标称供电电压 (Vsup)	2.5 V
表面贴装	NO
技术	CMOS
温度等级	COMMERCIAL
端子形式	NO LEAD
端子位置	DUAL

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HYS 72Dxx0x0GR

Registered DDR-I SDRAM-Modules

2.5 V 184-pin Registered DDR-I SDRAM Modules

256MB, 512MB & 1 GByte Modules

Preliminary Datasheet Rev. 0.99

• 184-pin Registered 8-Byte Dual-In-Line

DDR-I SDRAM Module for PC and Server

main memory applications

• One bank 32M

72, 64M x 72 and two bank

64M x 72, 128M

72 organization

• JEDEC standard Double Data Rate

Synchronous DRAMs (DDR-I SDRAM)

Single + 2.5 V (± 0.2 V) power supply

• Built with 256Mbit DDR-I SDRAMs in 66-

Lead TSOPII package

• Programmable CAS Latency, Burst Length,

and Wrap Sequence (Sequential &

Interleave)

• Performance:

-7

Component Speed Grade

Module Speed Grade

• Auto Refresh (CBR) and Self Refresh

• All inputs and outputs SSTL_2 compatible

• Re-drive for all input signals using register

and PLL devices.

• Serial Presence Detect with E

PROM

• Jedec standard MO-161 form factor:

133.35 mm

43.18 mm

4.00 mm

(8.00 mm when stacked)

• Jedec standard reference layout:

R/C A, R/C B and R/C C

• Gold plated contacts

-7.5

PC2100

133

100

-8

PC1600

125

100

Unit

DDR266A DDR266B DDR200

PC2100

143

133

MHz

Clock Frequency (max.) @ CL = 2.5

Clock Frequency (max.) @ CL = 2

The HYS 72Dxx0x0GR are industry standard 184-pin 8-byte Dual in-line Memory Modules (DIMMs)

organized as 32M

72, 64M

72 and 128M

72. The memory array is designed with Double Data

Rate Synchronous DRAMs for ECC applications. All control and address signals are re-driven on

the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive

loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling

capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a

serial E

PROM device using the 2-pin I

C protocol. The first 128 bytes are programmed with

configuration data and the second 128 bytes are available to the customer.

INFINEON Technologies

2.01

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