SFH6318T/6319T
Low Current, High Gain
Optocoupler
FEATURES
• Industry Standard SOIC-8 Surface Mountable
Package
• High Current Transfer Ratio, 800%
• Low Input Current, 0.5 mA
• High Output Current, 60 mA
• Isolation Test Voltage, 3000 V
RMS
• TTL Compatible Output, V
OL
=0.1 V
• Adjustable Bandwidth—Access to Base
• Underwriters Lab File #E52744
•
V
VDE 0884 Available with Option 1
D E
Package Dimensions in Inches (mm)
.120
±
.002
(3.05± .05)
.240
(6.10)
Pin 1
.192
±.005
(4.88±.13)
.004 (.10)
.008 (.20)
.021
(.53)
.050
(1.27)
typ.
NC 1
Anode 2
C .154±.002
L
(.391±.05) Cathode 3
.016
(.41)
NC 4
.015±.002
(.38±.05)
.008 (.20)
40
°
8 V
CC
7 V
B
6 V
0
5 GND
7°
.058
±.005
(1.49±.13)
.125
±.005
(3.18
±
.13)
APPLICATIONS
• Logic Ground Isolation—TTL/TTL, TTL/CMOS,
CMOS/CMOS, CMOS/TTL
• EIA RS 232C Line Receiver
• Low Input Current Line Receiver—Long Lines,
Party Lines
• Telephone Ring Detector
• 117 VAC Line Voltage Status Indication—Low
Input Power Dissipation
• Low Power Systems—Ground Isolation
DESCRIPTION
Very high current ratio together with 3000 V
RMS
isolation
are achieved by coupling an LED with an integrated
high gain photodetector in a SOIC-8 package. Separate
pins for the photodiode and output stage enable TTL
compatible saturation voltages with high speed opera-
tion. Photodarlington operation is achieved by tying the
V
CC
and
V
O
terminals together. Access to the base ter-
minal allows adjustment to the gain bandwidth.
The SFH6318T is ideal for TTL applications since the
300% minimum current transfer ratio with an LED cur-
rent of 1.6 mA enables operation with one unit load-in
and one unit load-out with a 2.2 k
Ω
pull-up resistor.
The SFH6319T is best suited for low power logic appli-
cations involving CMOS and low power TTL. A 400%
current transfer ratio with only 0.5 mA of LED current is
guaranteed from 0
°
C to 70
°
C.
Caution:
Due to the small geometries of this device, it should be han-
dled with Electrostatic Discharge (ESD) precautions. Proper
grounding would prevent damage further and/or degrada-
tion which may be induced by ESD.
5
°
max.
Lead
R.010 Coplanarity
.020±.004
(.25)
±.0015
(.04)
(.51±.10)
max. max.
2 plcs.
Tolerance:
±.005
(unless otherwise noted)
Maximum Ratings
(
T
A
=25
°
C
)
Emitter
Reverse Input Voltage ...................................................................3.0 V
Supply and Output Voltage,
V
CC
(pin 8-5),
V
O
(pin 6-5)
SFH6318T ...................................................................... –0.5 to 7.0 V
SFH6319T ....................................................................... –0.5 to 18 V
Input Power Dissipation..............................................................35 mW
Derate Linearly above ...............................................................50
°
C
Free Air Temperature ........................................................0.7 mW/
°
C
Average Input Current ................................................................ 20 mA
Peak Input Current ..................................................................... 40 mA
(50% Duty Cycle-1.0 ms pulse width)
Peak Transient Input Current
(t
p
≤
1.0
µ
s, 300 pps).................................................................. 1.0 A
Detector (Si Photodiode + Photodarlington)
Output Current
I
O
(pin 6)............................................................ 60 mA
Emitter-base Reverse Voltage (pin 5-7).........................................0.5 V
Output Power Dissipation.........................................................150 mW
Derate Linearly from 25
°
C ................................................2.0 mW/
°
C
Package
Storage Temperature ..................................................–55
°
C to +125
°
C
Operating Temperature ................................................–40
°
C to +85
°
C
Lead Soldering Temperature (t=10 s) .........................................260
°
C
Junction Temperature..................................................................100
°
C
Ambient Temperature Range .....................................–55
°
C to +100
°
C
Isolation Test Voltage between
Emitter and Detector........................................................ 3000 V
RMS
(refer to climate DIN 40046, part 2, Nov. 74)
Pollution Degree (DIN VDE 0110) ....................................................... 2
Creepage Distance ................................................................
≥
4.0 mm
Clearance ...............................................................................
≥
4.0 mm
Comparative Tracking Index
per DIN IEC 112/VDE 0303, part 1 .............................................. 175
Isolation Resistance
V
IO
=500 V,
T
A
=25
°
C R
ISOL
...................................................
≥
10
12
Ω
V
IO
=500 V,
T
A
=100
°
C R
ISOL
.................................................
≥
10
11
Ω
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2–282
Document Number: 83678
Revision 17-August-01
Electro-Optical Characteristics
(
T
A
=0
°
C
to 70
°
C
,
T
A
=25
°
C
—Typical, unless otherwise specified)
Parameter
Current Transfer Ratio
Symbol
CTR
—
Logic Low
Output Voltage
V
OL
—
Device
SFH6318T
SFH6319T
SFH6318T
SFH6319T
Min
300
400
500
—
Typ
1600
2000
1600
0.1
0.1
0.15
0.25
—
—
—
—
—
—
—
—
—
0.1
0.05
0.2
0.01
1.4
–1.8
25
10
12
10
11
0.6
Max
2600
3500
2600
0.4
0.4
0.4
0.4
250
100
1.5
10
1.7
—
—
—
—
mA
µA
V
mV/°C
pF
Ω
pF
µ
A
V
Units
%
Test Conditions
I
F
=1.6 mA,
V
O
=0.4 V,
V
CC
=4.5 V
I
F
=0.5 mA,
V
O
=0.4 V,
V
CC
=4.5 V
I
F
=1.6 mA,
V
O
=0.4 V,
V
CC
=4.5 V
I
F
=1.6 mA,
I
O
=4.8 mA,
V
CC
=4.5 V
I
F
=1.6 mA,
I
O
=8.0 mA,
V
CC
=4.5 V
I
F
=5.0 mA,
I
O
=15 mA,
V
CC
=4.5 V
I
F
=12 mA,
I
O
=24 mA,
V
CC
=4.5 V
I
F
=0 mA,
V
O
=
V
CC
=7.0 V
I
F
=0 mA,
V
O
=
V
CC
=18 V
I
F
=1.6 mA,
V
O
=OPEN,
V
CC
=18 V
I
F
=0 mA,
V
O
=OPEN,
V
CC
=18 V
I
F
=1.6 mA,
T
A
=25°C
I
F
=1.6 mA
f=1.0 MHz,
V
F
=0
V
IO
=500 VDC,
T
A
=25°C
V
IO
=500 VDC,
T
A
=100°C
f=1.0 MHz
3
3
—
2
Note
1,2
Logic High
Output Current
Logic Low Supply Current
Logic High Supply Current
Input Forward Voltage
Temperature Coefficient,
Forward Voltage
Input Capacitance
Resistance (Input-Output)
Capacitance (Input-Output)
I
OH
SFH6318T
SFH6319T
I
CCL
I
CCH
V
F
∆V
F
/∆T
A
C
IN
R
I-O
C
I-O
—
—
—
—
—
—
—
Switching Specifications
(
T
A
=25
°
C
)
Parameter
Propagation Delay Time
To Logic Low at Output
Symbol
t
PHL
Device
SFH6318T
SFH6319T
Propagation Delay Time
To Logic High at Output
t
PLH
SFH6318T
SFH6319T
Common Mode Transient Immunity
at Logic High Level Output
Common Mode Transient Immunity
at Logic Low Level Output
| CM
H
|
| CM
L
|
—
—
Min
—
—
—
—
—
—
Typ
2.0
6.0
0.6
2.0
4.0
1.5
1K
Max
10
25
1.0
35
60
7.0
—
—
V/µs
Units
µs
Test Conditions
I
F
=1.6 mA,
R
L
=2.2 kΩ
I
F
=0.5 mA,
R
L
=4.7 kΩ
I
F
=12 mA,
R
L
=270
Ω
I
F
=1.6 mA,
R
L
=2.2 kΩ
I
F
=0.5 mA,
R
L
=4.7 kΩ
I
F
=12 mA,
R
L
=270
Ω
I
F
=0 mA,
R
L
=2.2 kΩ
V
CM
=10 V
P–P
I
F
=1.6 mA,
R
L
=2.2 kΩ
V
CM
=10 V
P–P
2,4
—
2,4
5,6
Note
Notes
1. DC current transfer ratio is defined as the ratio of output collector current,
I
O
, to the forward LED input current,
I
F
times 100%.
2. Pin 7 open.
3. Device considered a two-terminal device: pins 1, 2, 3 and 4 shorted together and pins 5, 6, 7 and 8 shorted together.
4. Using a resistor between pin 5 and 7 will decrease gain and delay time.
5. Common mode transient immunity in logic high level is the maximum tolerable (positive) dV
cm
/dt on the leading edge of the common mode
pulse, V
CM
, to assure that the output will remain in a logic high state (i.e.
V
O
>2.0 V) common mode transient immunity in logic low level is the
maximum tolerable (negative) dV
cm
/dt on the trailing edge of the common mode pulse signal, V
CM
, to assure that the output will remain in a logic
low state (i.e.
V
O
<0.8 V).
6. In applications where dv/dt may exceed 50,000 V/
µ
s (such as state discharge) a series resistor, R
CC
should be included to protect
I
C
from
destructively high surge currents. The recommended value is
IV
-
R
CC
≅
------------------------------ kΩ
Refer to Figure 2.
0.15
I
(
mA
)
F
Document Number: 83678
Revision 17-August-01
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