AUSTIN SEMICONDUCTOR, INC.
AS42C4256 883C
256K x 4 VRAM
VRAM
AVAILABLE AS MILITARY
SPECIFICATION
MIL-STD-883
256K x 4 DRAM
WITH 512 x 4 SAM
PIN ASSIGNMENT (Top View)
28-Pin DIP
(400 MIL)
SC
SDQ1
SDQ2
TR\-OE\
DQ1
DQ2
ME\-WE\
NC
RAS\
A8
A6
A5
A4
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
SS
SDQ4
SDQ3
SE\
DQ4
DQ3
DSF
CAS\
QSF
A0
A1
A2
A3
A7
FEATURES
28-Pin SOJ
28-Pin LCC
SC
SDQ1
SDQ2
TR\-OE\
DQ1
DQ2
ME\-WE\
NC
RAS\
A8
A6
A5
A4
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
SS
SDQ4
SDQ3
SE\
DQ4
DQ3
DSF
CAS\
QSF
A0
A1
A2
A3
A7
Industry standard pinout, timing and functions
High-performance, CMOS silicon-gate process
Single +5V ±10% power supply
Inputs and outputs are fully TTL compatible
Refresh modes:RAS\ ONLY, CAS\-BEFORE-RAS\ (CBR)
and HIDDEN
512-cycle refresh within 8ms
Optional FAST PAGE MODE access cycles
Dual port organization: 256K x 4 DRAM port
512 x 4 SAM port
No refresh required for serial access memory
Low power: 15mW standby; 275mW active, typical
SPECIAL FUNCTIONS
JEDEC Standard Function set
PERSISTENT MASKED WRITE
SPLIT READ TRANSFER
WRITE TRANSFER/SERIAL INPUT
ALTERNATE WRITE TRANSFER
BLOCK WRITE
28-Pin DIP
(F-12)
SC
SDQ1
SDQ2
TR\-OE\
DQ1
DQ2
ME\-WE\
NC
RAS\
A8
A6
A5
A4
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
SS
SDQ4
SDQ3
SE\
DQ4
DQ3
DSF
CAS\
QSF
A0
A1
A2
A3
A7
OPTIONS
Timing [DRAM, SAM (cycle/access)]
100ns, 30ns/27ns
120ns, 35ns/35ns
80ns, 30ns/25ns
Packages
Ceramic SOJ
Ceramic DIP (400 mil)
Ceramic LCC
Ceramic Flat Pack
MARKING
-10
-12
-8
DCJ
C
EC
F
No.
No.
No.
No.
500
109
203
302
GENERAL DESCRIPTION
The AS42C4256 883C is a high-speed, dual port CMOS
dynamic random access memory or video RAM (VRAM) containing
1,048,576 bits. These bits may be accessed by a 4-bit wide DRAM
port or a 512 x 4-bit serial access memory (SAM) port. Data may
be transferred bidirectionally between the DRAM and the SAM.
The DRAM portion of the VRAM is functionally identical to
the AS4C4256 (256K x 4 DRAM). Four 512-bit data registers make
up the SAM portion of the VRAM. Data I/O and internal data
transfer are accomplished using three separate bidirectional data
paths; the 4-bit random access I/O port, the four internal 512 bit
wide paths between the DRAM and the SAM, and the 4-bit serial I/O
port for the SAM. The rest of the circuitry consists of the control,
timing and address decoding logic. Each port may be operated
asynchronously and independently of the other except when data is
being transferred
AS42C4256
883C
REV. 3/97
DS000016
3-27
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS42C4256 883C
256K x 4 VRAM
internally. As with all DRAMs, the VRAM must be re-
freshed to maintain data. Refresh cycles must be timed so
that all 512 combinations of
/
R
/
A
/
S addresses are executed at
least every 8ms, (regardless of sequence). Micron recom-
mends evenly spaced refresh cycles for maximum data
integrity. An internal transfer between the DRAM and the
SAM counts as a refresh cycle. The SAM portion of the
VRAM is fully static and does not require any refresh.
The operation and control of the AS42C4256 are opti-
mized for high performance graphics and communication
designs. The dual port architecture is well suited to buffer-
ing the sequential data used in raster graphics display,
serial and parallel networking and data communications.
Special features, such as SPLIT READ TRANSFER and
BLOCK WRITE allow further enhancements to system
performance.
FUNCTIONAL BLOCK DIAGRAM
4
COLUMN
MASK
COLUMN ADDRESS
LATCH/BUFFER
4
8
COLUMN DECODER
4
DRAM
OUTPUT
BUFFERS
9
DQ1
512
SENSE AMPLIFIERS
512
COLOR
REGISTER
M
A
S
K
4
WRITE
CONTROL
LOGIC
4
DQ4
4
MUX
4
4
ROW DECODER
ROW ADDRESS
LATCH/BUFFER
4
4
DRAM
INPUT
BUFFERS
4
A0-A8
9
9
512
512 x 512 x 4
DRAM ARRAY
MASK DATA
REGISTER
MASKED WRITE
CONTROL
LOGIC
BLOCK
WRITE
CONTROL
LOGIC
9
REFRESH
COUNTER
4
256
256
TIMING
GENERATOR
&
CONTROL
LOGIC
RAS
CAS
TR/OE
ME/WE
DSF
SC
SE
TRANSFER
GATE
LOWER
SAM
256
TRANSFER
GATE
UPPER
SAM
256
TRANSFER
CONTROL
SAM
OUTPUT
BUFFERS
SDQ1
SAM LOCATION
DECODER
SAM ADDRESS
LATCH/BUFFER
SAM ADDRESS
COUNTER
4
4
SAM
INPUT
BUFFERS
4
SDQ4
9
9
SPLIT SAM
STATUS & CONTROL
QSF
AS42C4256 883C
REV. 3/97
DS000016
3-28
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS42C4256 883C
256K x 4 VRAM
PIN DESCRIPTIONS
PIN
NUMBERS
1
4
SYMBOL
SC
/
T
/
R//O
/
E
TYPE
Input
Input
DESCRIPTION
Serial Clock: Clock input to the serial address counter for the SAM
registers.
Transfer Enable: Enables an internal TRANSFER operation at
/
R
/
A
/
S
(H
>
L), or
Output Enable: Enables the DRAM output buffers when taken LOW
after
/
R
/
A
/
S goes LOW (/C
/
A
/
S must also be LOW), otherwise the
output buffers are in a High-Z state.
7
?
M
/
E/?W
/
E
Input
Mask Enable: If
?
M
/
E/?W
/
E is LOW at the falling edge of
/
R
/
A
/
S a
MASKED WRITE cycle is performed, or
Write Enable:
?
M
/
E/?W
/
E is also used to select a READ (?
?
M
/
E/?W
/
E = H)
or WRITE (?
?
M
/
E/?W
/
E = L) cycle when accessing the DRAM. This
includes a READ TRANSFER (?
?
M
/
E/?W
/
E = H) or
WRITE TRANSFER (?
?
M
/
E/?W
/
E = L).
25
/
S
/
E
Input
Serial Port Enable:
/
S
/
E enables the serial I/O buffers and allows a
serial READ or WRITE operation to occur, otherwise the output
buffers are in a High-Z state.
/
S
/
E is also used during a WRITE
TRANSFER operation to indicate whether a WRITE TRANSFER or
a SERIAL INPUT MODE ENABLE cycle is performed.
Special Function Select: DSF is used to indicate which special
functions (BLOCK WRITE, MASKED WRITE vs. PERSISTENT
MASKED WRITE, etc.) are used on a particular access cycle.
Row Address Strobe:
/
R
/
A
/
S is used to clock-in the 9 row-address bits
and strobe the
?
M
/
E/?W
/
E,
/
T
/
R//O
/
E, DSF,
/
S
/
E,
/
C
/
A
/
S and DQ inputs. It
also acts as the master chip enable and must fall for initiation of any
DRAM or TRANSFER cycle.
Column Address Strobe:
/
C
/
A
/
S is used to clock-in the 9 column-
address bits, enable the DRAM output buffers (along with
/
T
/
R/?O
/
E),
and strobe the DSF input.
Address Inputs: For the DRAM operation, these inputs are multi-
plexed and clocked by
/
R
/
A
/
S and
/
C
/
A
/
S to select one 4-bit word out of
the 256K available. During TRANSFER operations, A0 to A8
indicate the DRAM row being accessed (when
/
R
/
A
/
S goes LOW) and
the SAM start address (when
/
C
/
A
/
S goes LOW).
DRAM Data I/O: Data input/output for DRAM cycles; inputs for
Mask Data Register and Color Register load cycles, and DQ and
Column Mask inputs for BLOCK WRITE.
Serial Data I/O: Input, output, or High-Z.
Split SAM Status: QSF indicates which half of the SAM is being
accessed. LOW if address is 0-255, HIGH if address is 256-511.
No Connect: This pin should be left either unconnected or tied to
ground.
Power Supply: +5V
±10%
Ground
22
DSF
Input
9
/
R
/
A
/
S
Input
21
/
C
/
A
/
S
Input
19, 18, 17,
A0-A8
Input
5, 6, 23, 24
DQ1-DQ4
Input/
Output
Input/
Output
Output
–
Supply
Supply
2, 3, 26, 27
20
8
14
28
AS42C4256 883C
REV. 3/97
DS000016
SDQ1-SDQ4
QSF
NC
V
CC
V
SS
3-29
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS42C4256 883C
256K x 4 VRAM
FUNCTIONAL DESCRIPTION
The AS42C4256 may be divided into three functional
blocks (see Figure 1): the DRAM, the transfer circuitry, and
the SAM. All of the operations described below are shown
in the AC Timing Diagrams section of this data sheet and
summarized in the Truth Table.
Note:
For dual-function pins, the function not being
discussed will be surrounded by parentheses. For
example, the
/
T
/
R/
/
O
/
E pin will be shown as
/
T
/
R/(
/
O
/
E) in
references to transfer operations.
The 18 address bits that are used to select a 4-bit word
from the 262,144 available are latched into the chip using
the A0-A8,
/
R
/
A
/
S and
/
C
/
A
/
S inputs. First, the 9 row-address
bits are set up on the address inputs and clocked into the
part when
/
R
/
A
/
S transitions from HIGH-to-LOW. Next, the
9 column address bits are set up on the address inputs and
clocked-in when
/
C
/
A
/
S goes from HIGH-to-LOW.
Note:
DRAM OPERATION
DRAM REFRESH
Like any DRAM based memory, the MT42C4256 VRAM
must be refreshed to retain data. All 512 row address
combinations must be accessed within 8ms. The MT42C4256
supports
/
C
/
A
/
S-BEFORE-/R
/
A
/
S,
/
R
/
A
/
S-ONLY and HIDDEN
types of refresh cycles.
For the
/
C
/
A
/
S-BEFORE-/R
/
A
/
S REFRESH cycle, the row ad-
dresses are generated and stored in an internal address
counter. The user need not supply any address data, and
simply must perform 512
/
C
/
A
/
S-BEFORE-/R
/
A
/
S cycles within
the 8ms time period.
The refresh address must be generated externally and
applied to A0-A8 inputs for
/
R
/
A
/
S-ONLY refresh cycles. The
DQ pins remain in a High-Z state for both the
/
R
/
A
/
S-ONLY
and
/
C
/
A
/
S-BEFORE-/R
/
A
/
S refresh cycles.
HIDDEN REFRESH cycles are performed by toggling
/
R
/
A
/
S (and keeping
/
C
/
A
/
S LOW) after a READ or WRITE
cycle. This performs
/
C
/
A
/
S-BEFORE-/R
/
A
/
S cycles but does not
disturb the DQ lines.
Any DRAM READ, WRITE, or TRANSFER cycle also
refreshes the DRAM row being accessed. The SAM portion
of the MT42C4256 is fully static and does not require any
refreshing.
DRAM READ AND WRITE CYCLES
The DRAM portion of the VRAM is nearly identical to
standard 256K x 4 DRAMs. However, because several of the
DRAM control pins are used for additional functions on
this part, several conditions that were undefined or in
“don’t care” states for the DRAM are specified for the
VRAM. These conditions are highlighted in the following
discussion. In addition, the VRAM has several special func-
tions that can be used when writing to the DRAM.
/
R
?
A
/
S also acts as a “master” chip enable for the
VRAM. If
/
R
?
A
/
S is inactive, HIGH, all other DRAM
control pins (
?
C
?
A
/
S,
/
T
/
R/
?
O
/
E,
?
M
/
E/
?
W
/
E, etc.) are “don’t
care” and may change state without effect. No DRAM
or TRANSFER cycles will be initiated without
/
R
?
A
/
S
falling.
For single port DRAMS, the
/
O
/
E pin is a “don’t care” when
/
R
/
A
/
S goes LOW. However, for the VRAM, when
/
R
/
A
/
S goes
LOW,
/
T
/
R/(/O
/
E) selects between DRAM access or TRANS-
FER cycles.
/
T
/
R/(/O
/
E) must be HIGH at the
/
R
/
A
/
S HIGH-to-
LOW transition for all DRAM operations (except
/
C
/
A
/
S-
BEFORE-/RA
/
S).
/
If (?M
/
E)/?W
/
E is HIGH when
/
C
/
A
/
S goes LOW, a DRAM
READ operation is performed and the data from the memory
cells selected will appear at the DQ1-DQ4 port. The (/T
/
R)/
/
O
/
E input must transition from HIGH-to-LOW some time
after
/
R
/
A
/
S falls to enable the DRAM output port.
For single port normal DRAMs,
?
W
/
E is a “don’t care”
when
/
R
/
A
/
S goes LOW. For the VRAM,
?
M
/
E/(?W
/
E) is used,
when
/
R
/
A
/
S goes LOW, to select between a MASKED WRITE
cycle and a normal WRITE cycle. If
?
M
/
E/(?W
/
E) is LOW at the
/
R
/
A
/
S HIGH-to-LOW transition, a MASKED WRITE opera-
tion is selected. For any DRAM access cycle (READ or
WRITE),
?
M
/
E/(?W
/
E) must be HIGH at the
/
R
/
A
/
S HIGH-to-
LOW transition. If (?M
/
E)/?W
/
E is LOW before
/
C
/
A
/
S goes
LOW, a DRAM EARLY-WRITE operation is performed and
the data present on the DQ1-DQ4 data port will be written
into the selected memory cells. If (?M
/
E)/?W
/
E goes LOW after
/
C
/
A
/
S goes LOW, a DRAM LATE-WRITE operation is per-
formed. Refer to the AC timing diagrams.
The VRAM can perform all the normal DRAM cycles
including READ, EARLY-WRITE, LATE-WRITE,
READ-MODIFY-WRITE, FAST-PAGE-MODE READ,
FAST-PAGE-MODE WRITE (Late or Early), and FAST-
PAGE-MODE READ-MODIFY-WRITE. Refer to the AC
timing parameters and diagrams in the data sheet for more
details on these operations.
AS42C4256 883C
REV. 3/97
DS000016
3-30
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
NONPERSISTENT MASKED WRITE
The MASKED WRITE feature eliminates the need for a
READ-MODIFY-WRITE cycle when changing only specific
bits within a 4-bit word. The MT42C4256 supports two
types of MASKED WRITE cycles, NONPERSISTENT
MASKED WRITE and PERSISTENT MASKED WRITE.
If
?
M
/
E/(?W
/
E) and DSF are LOW at the
/
R
/
A
/
S HIGH-to-
LOW transition, a NONPERSISTENT MASKED WRITE is
performed and the data (mask data) present on the DQ1-
DQ4 inputs will be written into the mask data register. The
mask data acts as an individual write enable for each of the
four DQ1-DQ4 pins. If a LOW (logic “0”) is written to a
mask data register bit, the input port for that bit is disabled
during the subsequent WRITE operation and no new data
will be written to that DRAM cell location. A HIGH (logic
“1”) on a mask data register bit enables the input port and
allows normal WRITE operation to proceed. Note that
/
C
/
A
/
S
is still HIGH. When
/
C
/
A
/
S goes LOW, the bits present on the
DQ1-DQ4 inputs will be either written to the DRAM (if the
mask data bit is HIGH) or ignored (if the mask data bit is
LOW). The DRAM contents that correspond to masked
input bits will not be changed during the WRITE cycle. The
MASKED WRITE is nonpersistent (must be re-entered at
every
/
R
?
A
/
S cycle) if DSF is LOW when
/
R
?
A
/
S goes LOW. The
mask data register is cleared at the end of every NONPER-
SISTENT MASKED WRITE. FAST PAGE MODE can be
used with NONPERSISTENT MASKED WRITE to write
several column locations in an addressed row. The same
mask is used during the entire FAST-PAGE-MODE
/
R
/
A
/
S
cycle. An example NONPERSISTENT MASKED WRITE
cycle is shown in Figure 1.
NONPERSISTENT MASKED WRITE
RAS
NONPERSISTENT MASKED WRITE
CAS
ME/WE
DSF
STORED
DATA
1
1
0
0
BEFORE
MASK
0
1
0
1
,, ,, ,,,
,, ,, ,
,
,
,
INPUT
X
0
X
1
STORED STORED
MASK
DATA
DATA (RE-WRITE)
1
0
0
1
AFTER
0
0
0
0
BEFORE
0
1
0
1
STORED
X
1
STORED
DATA
0
1
0
1
AFTER
ADDRESS 0
ADDRESS 1
X = NOT EFFECTIVE (DON’T CARE)
,,
X
1
DON’T CARE
Figure 1
NONPERSISTENT MASKED WRITE EXAMPLE
MT42C4256 883C
REV. 3/97
DS000016
3-31
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
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