SB-36110VX
Make sure the next
Card you purchase
®
has...
VME Compatible Twelve Channel
Synchro/Resolver-to-Digital Converter
FEATURES
•
Up to 12 Independent Converter
Channels
•
Accepts Synchro or Resolver Inputs
•
±1 min Accuracy
•
Synthesized Reference
•
Software Controlled Self Test for:
0°, 45°, and 90°
•
Software Programmable Resolution
and Bandwidth
•
16-, 24-, and 32-Bit Addressing Modes
•
Commercial and Ruggedized
Industrial Versions
•
VxWorks® Driver Included
DESCRIPTION
The SB-36110VX is a 12 channel, 6U, B size, VME synchro card
which can be configured for either 3, 6, 9, or 12 channels of fully inde-
pendent Synchro-to-Digital or Resolver-to-Digital conversion. For
each channel, the conversion process is implemented using a DDC
RDC-19222S, 16-bit monolithic converter and a thin film resistor net-
work.
Each converter can be configured for a 11.8 V line-to-line
Synchro/Resolver, 90 V line-to-line Synchro, or 2 V SIN/COS signal
input, with a 10-, 12-, 14-, or 16-bit resolution. The user is provided
with two operating frequency ranges. The low carrier frequency card
option operates from 47 Hz to 5 kHz and is software programmable
for bandwidths of 15 Hz or 45 Hz. The high carrier frequency card
option operates from 360 Hz to 5 kHz and is software programmable
for bandwidths of 80 Hz or 300 Hz. The card has a synthesized refer-
ence and ±1 minute accuracy.
Separate reference inputs are provided for each group of three con-
verters (four reference groups for the 12 channels). Signal and refer-
ence inputs are available through the front panel D connectors or
through the P2 VME Connector.
APPLICATIONS
The SB-36110VX is designed for modern, high performance industri-
al and military control systems.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
©
2000 Data Device Corporation
S/R Input 1
S/R Converter 1
S/R Input 2
Data Device Corporation
www.ddc-web.com
S/R Input 3
Ref for 1, 2, 3
S/R Converter 2
S/R Converter 3
FRONT
PANEL
I/O
I/O
JUMPER
BLOCK
S/R Input 4
S/R Input 5
S/R Input 6
Ref for 4, 5, 6
S/R Input 7
S/R Input 8
S/R Input 9
Ref for 7, 8, 9
S/R Input 10
S/R Input 11
S/R Input 12
Ref for 10, 11, 12
S/R Converter
4, 5, 6
CONNECTOR
J2, J3
VME
P2
CONNECTOR
2
S/R Converter
7, 8, 9
ADDRESS
JUMPER
BLOCK
S/R Converter
10, 11, 12
LOGICAL ADDRESS
SWITCHES
VME
CONFIGURATION
REGISTERS
DATA BUS
VME
BACKPLANE
INTERFACE
STATUS
REGISTER
CONTROL
REGISTER
VME
BACKPLANE
SB-36110VX
H-01/06-0
FIGURE 1. SB-36110VX BLOCK DIAGRAM
TABLE 1. SB-36110VX SPECIFICATIONS
These specifications apply over the rated power supply, temperature,
and reference frequency ranges; and 10% signal amplitude and
10% harmonic distortion.
PARAMETER
RESOLUTION
ACCURACY
REPEATABILITY
DIFFERENTIAL LINEARITY
REFERENCE INPUT (RH, RL)
Type
Voltage Range
Input Impedance
single ended
differential
Frequency Range
Low Carrier Frequency Card
High Carrier Frequency Card
SIGNAL INPUT
CHARACTERISTICS
Synchro Input (L-L)
Zin line-to-line
Zin line-to-ground
Resolver Input (L-L)
Zin single ended
Zin differential
Common Mode Voltage
DYNAMIC CHARACTERISTICS
Selectable Bandwidths
Low Carrier Frequency Card
High Carrier Frequency Card
ANALOG OUTPUTS
VELOCITY (VEL)
POWER SUPPLY
Nominal Voltage
Typical Current Draw
no converters
12 converters
TEMPERATURE RANGE
Operating (-3 option)
(-2 option)
Storage
(-3 option)
(-2 option)
PHYSICAL CHARACTERISTICS
Size
Weight
V
mA
mA
°C
°C
°C
°C
+5
500
700
Hz
Hz
Vrms
Ohms
Ohms
Hz
Hz
UNIT
Bits
Min.
LSB
LSB
VALUE
10, 12, 14, or 16
1 + 1 LSB (Note 1)
1 max.
1 max.
Each Channel
Differential
10 - 28
90k min.
180k min.
40 - 130
450k min.
900k min.
TABLE 2A. DYNAMIC CHARACTERISTICS
360 HZ TO 5 KHZ CARD
PARAMETER
Resolution
Tracking Rate
UNIT
BW1
12*
288
300
506k
1.7
296k
711.7
355.8
44.6k
12.9
BW2
10*
320
80
31.6k
0.44
81.6k
177.7
88.9
11.1k
40.9
12*
80
80
31.6k
0.44
81.6k
177.7
88.9
2.8k
51.2
14
20
80
31.6k
0.44
81.6k
177.7
88.9
695
81.1
16
5
80
31.6k
0.44
81.6k
177.7
88.9
173.7
161
14**
72
300
506k
1.7
296k
711.7
355.8
11.1k
20.9
16**
18
300
506k
1.7
296k
711.7
355.8
2.8k
43.0
bits
10*
rps min. 1152
(typ)
BW (Closed Loop)
Hz nom. 300
Ka
506k
1/sec
2
A1
1.7
1/sec
A2
296k
1/sec
A
711.7
1/sec
B
355.8
1/sec
Acceleration (1 LSB lag) deg/sec 178.3k
Settling Time
ms typ. 10.2
(179 deg. step)
PARAMETER
Resolution
Tracking Rate
UNIT
bits
rps min.
(typ)
BW (Closed Loop)
Hz nom.
Ka
1/sec
2
1/sec
A1
1/sec
A2
1/sec
A
1/sec
B
Acceleration (1 LSB lag) deg/sec
ms typ.
Settling Time
(179 deg. step)
*
47 - 5k
360 - 5k
V
Ohms
Ohms
V
Ohms
Ohms
V max.
N/A
11.8
N/A
52k
N/A
35k
2
11.8
10M min. 70k
in ||10 pF
N/A
140k
N/A
30
90
195k
130k
90
260k
520k
180
Exceeds tracking rate to bandwidth ratio. Selecting a bandwidth that is too
low relative to the maximum application tracking rate can create a spin-around
condition in which the converter never settles (particularly during initial power
-up.) (Refer to “Tracking/BW Relationship” table in RDC-19222S data sheet.)
** Converters may jitter at carrier frequencies < 1.5 kHz, due to bandwidth selected.
See TABLES 2A & 2B
15
80
45
300
TABLE 2B. DYNAMIC CHARACTERISTICS
47 HZ TO 5 KHZ CARD
PARAMETER
Resolution
Tracking Rate
UNIT
12*
40
45
10.13k
0.25
41.03k
100
50
891.4
92
BW2
12*
8
15
1.11k
0.14
8.16k
33.3
16.7
97.71
302
14
2
15
1.11k
0.14
8.16k
33.3
16.7
24.43
549
16
0.5
15
1.11k
0.14
8.16k
33.3
16.7
6.11
1325
BW1
14**
10
45
10.13k
0.25
41.03k
100
50
222.9
149
16**
2.5
45
10.13k
0.25
41.03k
100
50
55.7
308
bits
10*
rps min. 160
(typ)
BW (Closed Loop)
45
Hz nom.
2
10.13k
Ka
1/sec
1/sec
A1
0.25
1/sec 41.03k
A2
1/sec
A
100
1/sec
B
50
Acceleration (1 LSB lag) deg/sec 3.57k
ms typ.
Settling Time
73
(179 deg. step)
PARAMETER
Resolution
Tracking Rate
UNIT
bits
10*
rps min.
32
(typ)
BW (Closed Loop)
15
Hz nom.
2
Ka
1.11k
1/sec
1/sec
A1
0.14
1/sec
A2
8.16k
1/sec
A
33.3
1/sec
B
16.7
Acceleration (1 LSB lag) deg/sec 390.83
ms typ.
Settling Time
226
(179 deg. step)
*
See TABLE 3
+12 (Note 2)
---
---
0 to +70
-40 to +85
-30 to +85
-55 to +100
-12
60
260
inches
(mm)
lbs (kg)
9.187 x 6.300
(233.5 x 160.02)
0.9 (0.4)
Notes:
1. Includes 1 bit of jitter in 16-bit mode.
2. The +12V power supply is only used for transient protection of the discrete
I/O. There is a 33V zener diode between the common inputs of the discrete
power supply and the +12V power supply.
Exceeds tracking rate to bandwidth ratio. Selecting a bandwidth that is too
low relative to the maximum application tracking rate can create a spin-around
condition in which the converter never settles (particularly during initial power
-up.) (Refer to “Tracking/BW Relationship” table in RDC-19222S data sheet.)
** Converters may jitter at carrier frequencies < 225 Hz, due to bandwidth selected.
Data Device Corporation
www.ddc-web.com
3
SB-36110VX
H-01/06-0
TABLE 3. VELOCITY CHARACTERISTICS
PARAMETER
Polarity
Voltage Range
Voltage Scaling
(resolution
dependent)
Scale Factor
Error
Scale Factor TC
Reversal Error
Linearity
Zero Offset
Zero Offset TC
Load
UNITS
V
RPS/V
TYPICAL
4.0
Tracking Rate
Typical (See TABLE 2A & 2B)
4
10
100
1
0.5
5
15
20 (max.)
200 (max.)
2 (max.)
1 (max.)
15 (max.)
30 (max.)
10 (min.)
MAX./MIN.
Each channel's operating parameters are set by means of bits
28 to 30 which are read/write bits. Bit 30 determines the band-
width and bits 28 and 29 determine the resolution (See the
RDC-19222S Series data sheet).
The register space between offsets 0x30 and 0x3b is reserved
for testing purposes and their outputs are unspecified.
The control and status register is located at offset 0x3c.
Read/write bits 0 to 11 control the INH signals of the respective
channels and should be set before reading the channel and
cleared between reads. Bit 13 invokes the self test mode while
bits 14 and 15 control the DC signals applied to the COS and
SIN inputs when in the test mode (see Wrap-Around Self-Test
section below).
%
PPM/ deg C
%
% output
mV
µV/ deg C
k Ohms
INTRODUCTION
The SB-36110VX card contains up to 12 channels of
Synchro/Resolver-to-Digital converters sharing 4 sets of refer-
ence signals; each reference is allocated to three input channels.
Selection of reference configuration and other hardware operat-
ing characteristics is carried out by means of jumpers and resis-
tor network position.
Each channel and its associated operating control and BIT func-
tions are grouped together into a set of 32-bit (4-byte) read/limit-
ed-write registers occupying a total of 64 bytes of memory-
mapped address space. This register block is placed in the VME
address space by means of 3 eight-section DIP switches repre-
senting address lines 8 to 31. Control and status information is
held in a register located at the top of the address space
(address offset 0x3c). There are 3 unused register locations.
WRAP-AROUND SELF-TEST
Bits 15, 14 and 13 in the control register are used to place the
card into a self-test mode. This test mode is an intrusive test
(that is it interrupts the incoming data to the converters) and it is
operative on all channels simultaneously.
When Bit 13 is On (logic “1”), the card is placed into the self-test
mode. This disconnects the signal inputs from SIN/COS and
instead applies the DC test signals switched by control bits 14
and 15. The logic value of bits 14 and 15 determines the angle
read by the converters (see TABLE 4). Bit 14 controls the COS
input and bit 15 controls the SIN input.These signals are either
at the internal reference level (approximately 2 V) or at zero cor-
responding to the control bit state
ACCESS MODES
The card can be operated in 16-, 24-, or 32-bit address modes.
Selection of the address mode is set by two jumpers, JP1 (3) and
JP1 (2) which disable address lines A24-31 and A16-31 respec-
tively and set the AM0-5 combination to which the card will
respond with the selected address line combination. Operation in
protected mode is possible and is invoked by using jumper
JP1 (1). When this jumper is connected, the processor can only
access the card when in supervisor mode; otherwise the card
can be accessed in either supervisor or user mode. See TABLE
5 for a summary of jumper connections.
BIT 15
X
0
0
1
1
TABLE 4. CONVERTER ANGLE READ
IN SELF-TEST MODE
BIT 14
X
0
1
0
1
BIT 13
0
1
1
1
1
ANGLE
Input
Invalid Angle
0 degrees
90 degrees
45 degrees
X = Don’t Care
The converter BIT for all converters will be on when in test mode.
BUILT IN TEST (BIT)
The BIT from each converter is returned as the Most Significant
Bit (MSB) of each 32-bit channel register. It should be noted that
the signal is inverted for convenience in software so that a logic
one indicates a tracking failure and returns a negative value in a
32-bit read. In addition, a read of the control register will also pro-
vide the BIT from all the converters with Bit 31 being the
logical OR of all the converter BIT’s output. This provides the
user with a simple way of testing the BIT during a read. The user
can do this by testing the read data to see if it is negative.
SB-36110VX
H-01/06-0
REGISTER MODEL
Each of the first twelve registers, addressed at offsets 0x00,
0x04, and 0x2c, read and control one RDC channel. The Most
Significant Bit (MSB/bit 31) is the inverted BIT output from the
channel so that a returned negative value indicates an unstable
signal. The result of the conversion appears in the least signifi-
cant 16 bits of the register. These are all read-only bits.
Data Device Corporation
www.ddc-web.com
4
ADDRESS CONFIGURATION
The SB-3611X card requires that the user program the base
address by setting jumpers and DIP switches on the card.
Before installing the SB-3611X card, refer to FIGURE 3 for DIP
Switch Configuration and FIGURE 4 for Reference Jumper
Selection.
The SB-3611X card can be operated in 16-, 24- or 32-bit
address modes (See FIGURE 2). Selection of the address mode
is set by two jumpers, JP1 (3) and JP1 (2), which when made
disable address lines A24-31 and A16-31 respectively and set
the AM0-5 combination to which the card will respond with the
selected address line combination. The card is in 32-bit address
mode when jumpers JP1 (2) and JP1 (3) are not installed.
Operation in protected mode is possible and is invoked by
installing jumper JP1 (1). When this jumper is connected, the
processor can only access the card when in supervisor mode;
otherwise the card can be accessed in either supervisor or user
mode.
MSB
LSB
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
* SW1
8 7 6 5 4 3 2 1
A15
ON
A8
A0 - A7
Hard Coded
for
0000 0000
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Binary
8
0
0
0
Hex
C3
VME_RDC_EPLD1
C4
C54
C53
C5
C52
C6
JP1
C7
C8
C36
J1
4
3
2
1
P1
C14
SW1
C16
C18
C15
C17
A23
C36
JP1
4
3
2
1
C13
C20
C19
SW2
JP1(4)
JP1(3)
JP1(2)
JP1(1)
C22
C21
C7
A31
C14
C6
C24
C23
C3
SW3
C4
C54
C5
C53
C52
C30
C29
P1
FIGURE 2. 16/24/32 BIT ADDRESS
JUMPER CONFIGURATION
TABLE 5. JP1 ADDRESSING MODE
JUMPER SELECTION
JP1 (1) JP1 (2) JP1 (3)
Off
On
Off
On
Off
On
Off
Off
On
On
Off
Off
On
On
X
X
Off
Off
DESCRIPTION
A24 non-privileged data access
A24 supervisory data access
A16 non-privileged data access
A16 supervisory data access
A32 non-privileged data access
A32 supervisory data access
AM CODE
39
3D
29
2D
09
0D
FIGURE 3. ADDRESS DIP SWITCH
CONFIGURATION
1. X = Don’t care.
2. When JP1(2) is linked the use of JP1(3) is “don’t care”.
Data Device Corporation
www.ddc-web.com
5
ON
J1
ON
VME_RDC_EPLD1
C8
ON
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
*Note: ON = Logic 0
OFF = Logic 1
"Reverse Logic"
A16
A24
The Address of the SB-3611X in the example shown in FIGURE
3 is set to HEX address 8000 (in 16-Bit address mode). The user
may choose from 0000 0000h to FFFF FF00h in 100 HEX incre-
ments.
C13
A15
A8
1 2 3 4 5 6 7 8
U1
U2
U3
SB-36110VX
H-01/06-0
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
