A3942
Quad High-Side Gate Driver
for Automotive Applications
Features and Benefits
▪
Drives four N-channel high-side MOSFETS
▪
Charge pump for 100% duty cycle operation
▪
Serial and discrete inputs
▪
SPI port for control and fault diagnostics
▪
4.5 to 60 V input voltage range
▪
Sleep function for minimum power drain
▪
Thin profile 38-lead TSSOP with internally fused leads for
enhanced thermal dissipation
▪
Lead (Pb) free
▪
Device protection features:
▫
Short-to-ground detection (latched)
▫
Short-to-battery protection (latched)
▫
Open load detection (latched)
▫
V
DD
undervoltage lockout
▫
V
CP
undervoltage lockout
▫
Thermal monitor
Description
The A3942 is a highly-integrated gate driver IC that can drive
up to four N-Channel MOSFETs in a high-side configuration.
The device is designed to withstand the harsh environmental
conditions and high reliability standards of automotive
applications.
Serial Peripheral Interface (SPI) compatibility makes the device
easily integrated into existing applications. The MOSFETs in
such applications are typically used to drive gasoline or diesel
engine management actuators, transmission actuators, body
control actuators and other general-purpose automotive or
industrial loads. In particular, the A3942 is suited for driving
glow plugs, valves, solenoids, and other inductive loads in
engine management and transmission systems.
The device is available in a 38-lead thin (1.20 mm maximum
overall height) TSSOP package with six pins that are fused
internally to provide enhanced thermal dissipation (package
LG). It is lead (Pb) free with 100% matte tin leadframe
plating.
Package: 38 pin TSSOP (suffix LG)
Approximate Scale 1:1
Typical Application
V
DD
CP1 CP2
VDD
IREF
VREG
D1
CP3 CP4
VCP
VBB
V
BAT
FAULTZ
SDO
SDI
System
Control
Logic
CSZ
SCLK
RESETZ
ENB
IN1
IN2
IN3
IN4
A3942
G1
S1
D2
G2
S2
D3
G3
S3
D4
G4
GND GND GND GND GND GND S4
3942-DS, Rev. 2
A3942
Quad High-Side Gate Driver
for Automotive Applications
Selection Guide
Part Number
Packing*
Package
38-pin TSSOP with six internally-fused pins
for enhanced thermal dissipation
A3942KLG-T
50 pieces per tube
A3942KLGTR-T
4000 pieces per reel
*Contact Allegro for additional packing options
Absolute Maximum Ratings
Characteristic
VBB, CP1, CP3 Pins Voltage
Dx (Drain Detect) Pins Voltage
Sx (Output Source) Pins Voltage
VCP, CP2, CP4, Gx Pins Voltage
All Other Pins
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
ESD Rating, Human Body Model
ESD Rating, Charged Device Model
T
A
T
J
(max)
T
stg
AEC-Q100-002, all pins
AEC-Q100-011, all pins
Range K
V
Dx
V
Sx
Symbol
Notes
Rating
–0.3 to 60
V
BB
– 6 V
to V
BB
+ 0.5 V
–10 to 60
–0.3 to 74
–0.3 to 7
–40 to 125
150
–55 to 150
2500
1050
Units
V
V
V
V
V
ºC
ºC
ºC
V
V
Thermal Characteristics
Characteristic
Package Thermal Resistance, Junction
to Ambient
Symbol
R
θJA
Test Conditions*
4-layer PCB based on JEDEC standard, with no
thermal vias
Rating
47
Units
ºC/W
*For additional information, refer to the Allegro website.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A3942
Quad High-Side Gate Driver
for Automotive Applications
Functional Block Diagram
CP4
CDD
VDD
CP3
C34
Charge
Pump
IREF
60.4 kΩ CREF
CP2
C12
CP1
Reference
Current
V
DD
UVLO
Thermal
Warning
V
CP
UVLO
VCP
CCP
FAULTZ
Fault
Monitor
U
V Internal
L Regulator
O
V
DD
VBB
CBB2
CBB1
SDO
VREG
CREG
SDI
CSZ
Voltage to VBB pin
and to Qx MOSFETs
must come from
the same supply
RDx
Dx
SCLK
RESETZ
Control
Logic
V
ds
Monitor
One of Four
High-Side Drivers
ENB
V
CP
IN1
IN2
High
Side
Driver
RGx
Gx
Qx
IN3
IN4
Open
Load
Detect
RSx
Sx
L
GND
GND
GND
GND
GND
GND
L
Name
CBB1
CBB2
CCP
CDD
CREF
CREG
RSx
Suitable Characteristics
47
μF,
63 V, electrolytic
0.22
μF,
100 V, X7R ceramic
1
μF,
16V, X7R ceramic
0.47
μF,
16 V, X7R ceramic
47 pF, 16 V, X7R ceramic
0.22
μF,
16 V, X7R ceramic
0
Ω ≤
R
≤
100
Ω
Representative Device
EGXE630ELL470MJC5S
C12, C34 0.33
μF
or 0.47
μF,
25 V, X7R ceramic
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A3942
Quad High-Side Gate Driver
for Automotive Applications
ELECTRICAL CHARACTERISTICS
Valid at –40°C
≤
T
J
≤
150°C, C12 = C34 = 0.47
μF,
CCP = 1
μF,
R
REF
= 60.4 kΩ, and
V
BB
within limits, unless otherwise noted
Characteristics
Supplies and Regulators
Operating Voltage
V
BB
Charge pump on,
outputs disabled
Sleep mode
Logic Supply (voltage supplied to
logic circuits)
Logic Supply Current
Logic Supply UVLO Threshold
Logic Supply UVLO Hysteresis
Charge Pump Switching Frequency
Charge Pump Output Voltage
Charge Pump UVLO
Internal Regulator Voltage
Regulator Voltage UVLO
Regulator Voltage UVLO Hysteresis
Control Circuits
Current Reference Source Voltage
Master Reset Pulse
Sleep Command
Wake-Up Delay
Logic I/O
Logic Input Voltage, High
Logic Input Voltage, Low
V
IH
V
IL
0.7 ×
V
DD
0
–
–
V
DD
0.3 ×
V
DD
V
V
V
REF
t
RESET
t
SLEEP
t
WAKE
RESETZ pin pulsed low
RESETZ pin held low
RESETZ pin held high; CCP = 1
μF
1.14
0.3
20
–
1.2
–
–
–
1.26
5
–
2
V
μs
μs
ms
V
DD
I
DD
V
DD(UV)
V
DD(hys)
f
CP
V
CP
V
CP(UV)
V
REG
V
REG(UV)
V
REG(hys)
Measured relative to
VBB pin
V
BB
= 12 V, I
CP
= 10 mA
V
BB
= 6.0 V, I
CP
= 5 mA
V
BB
= 4.5 V, I
CP
= 5 mA
V
DD
= 5.5 V, serial port switching
V
DD
= 5.5 V, device quiescent or in sleep mode
V
DD
falling, FAULTZ pin held active (low) for
1.5 V
≤
V
DD
≤
V
DDUV
V
BB
= 60 V
V
BB
= 36 V
V
BB
= 36 V
V
BB
= 36 V, T
J
= 25°C
4.5
–
–
–
–
3
–
–
2.6
100
–
10
10
7
5.1
–
3
100
–
–
–
–
–
–
–
–
–
150
100
–
–
–
–
4
–
–
60
10
8
15
1
5.5
3
0.5
2.9
200
–
13
13
11
5.8
–
3.8
400
V
mA
mA
μA
μA
V
mA
mA
V
mV
kHz
V
V
V
V
V
V
mV
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Quiescent Current
I
BB(Q)
Relative to VBB pin, V
CP
falling
CREG = 0.22
μF
V
REG
falling
Continued on the next page...
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A3942
Quad High-Side Gate Driver
for Automotive Applications
ELECTRICAL CHARACTERISTICS (continued)
Valid at –40°C
≤
T
J
≤
150°C, C12 = C34 = 0.47
μF,
CCP = 1
μF,
R
REF
= 60.4 kΩ, and V
BB
within limits, unless otherwise noted
Characteristics
Logic Input Hysteresis
Symbol
V
hys
CSZ pin
I
I(HI)
Logic Input Current
1
I
I(LO)
SDI and SCLK Pins
All other pins
CSZ pin
SDI and SCLK Pins
All other pins
Logic Output Voltage, SDO Pin
(CMOS push-pull circuit)
FAULTZ Pin Active (Low) Voltage
FAULTZ Pin Inactive (High) Current
Drivers
Gate Voltage, High
Gate Voltage, Low
V
G(HI)
V
G(LO)
I
G(HI)
Peak Gate Current
1,2
I
G(LO)
Propagation Delay
Gate-to-Source Resistance
Gate-to-Source Zener Diode Voltage
Drain Leakage Current
t
p(on)
t
p(off)
R
GS
V
GS(Z)
I
Dlkg
Measured relative to Sx pin, capacitive load–fully
charged
Measured relative to Sx pin, capacitive load–fully
discharged
R
G
= 0
Ω,
1 V
≤
V
GS
≤
4 V, V
Sx
= V
BB
V
BB
= 4.5 V, V
CP
= 9 V
V
BB
≥
9 V, V
CP
= 13 V
V
CP
–1
–
–10
–15
10
25
–
–
300
15
–
–
–
T
J
= 150°C
T
J
= 25°C
–
–
–
–
–
–
0.6
0.6
500
–
–
–
–
V
CP
0.1
–
–
–
–
–
–
800
18
10
5
1
V
V
mA
mA
mA
mA
μs
μs
kΩ
V
μA
μA
μA
V
OUT(HI)
V
OUT(LO)
V
FAULTZ(LO)
I
FAULTZ(HI)
I
OUT
= –1 mA
I
OUT
= 1 mA
I
FAULTZ
= 1 mA, V
DD
= 1.5 V, V
BB
= 4.5 V
V
FAULTZ
= 5 V
V
I
= 0 V
V
I
= V
DD
= 5.5 V
Test Conditions
Min.
0.1 ×
V
DD
–
–
–
–
–
–
–
–
–
–
Typ.
–
–
–
–
–
–
–
V
DD
– 0.5
–
–
–
Max.
–
10
5
100
–100
–5
–10
V
DD
0.4
0.4
10
Units
V
μA
μA
μA
μA
μA
μA
V
V
V
μA
R
G
= 0
Ω,
V
GS
= 1 V, V
Sx
= 0 V
R
G
= 0
Ω,
2 V
≤
V
GS
≤
4 V, V
Sx
= 0 V
From 90% V
INx
to V
Gx
– V
Sx
= 200 mV
From 10% V
INx
to V
CP
– V
Gx
= 200 mV
RESETZ pin held low; V
GSZ
= 10 V
I
G
= 2 mA
RESETZ pin held low, V
BB
= V
Dx
= 60 V
RESETZ pin held low,
V
BB
= V
Dx
= 36 V
Continued on the next page...
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
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