2N7002FN3
60V N-CHANNEL ENHANCEMENT MODE MOSFET
FEATURES
• R
DS(ON)
, V
GS
@10V,I
DS
@500mA=5Ω
• R
DS(ON)
, V
GS
@4.5V,I
DS
@50mA=7.5Ω
• Advanced Trench Process Technology
• High Density Cell Design For Ultra Low On-Resistance
• Specially Designed for Battery Operated Systems, Solid-State
Relays Drivers : Relays, Displays, Lamps, Solenoids, Memories, etc.
• In compliance with EU RoHS 2002/95/EC directives
DFN 3L
0.042(1.05)
0.037(0.95)
0.026(0.65)
0.021(0.55)
Unit : inch(mm)
0.0 22 (0.55)
0.047(0.45)
0.002(0.05) MAX.
MECHANICAL DATA
• Case: DFN 3L, Plastic
• Terminals: Solderable per MIL-STD-750, Method 2026
• Marking: AH
0.013(0.32)
0.008(0.22)
0.022(0.55)
0.047(0.45)
0.014(0.36)
0.013(0.32)
0.008(0.22)
0.0 14 (0.20)
0.0 08 (0.20)
0.004(0.10)
0.0 08 (0.20)
3
2
1
Maximum Ratings and Thermal Characteristics (T
A
=25
O
C unless otherwise noted )
PARAMETER
Drain-Source Voltage
Gats-Source Voltage
Continous Drain Current
Pulsed Drain Current
(1)
SYMBOL
V
DS
V
GS
I
I
LIMIT
60
+20
115
800
0.004(0.10)
UNITS
V
V
mA
mA
D
DM
Maximum Power Dissipation
Junction-to Ambient Thermal Resistance (PCB mounted)
2
O p e ra t i ng J unc t i o n a nd S t o ra g e Te mp e r a tur e Ra ng e
P
D
150
mW
o
R
θJA
T
J
, T
S TG
883
-55 to +150
C/W
o
C
Note 1 : Maximum DC current limited by the package
2 : Surface mounted on FR4 board,t<10 sec
PAN JIT RESERVES THE RIGHT TO IMPROVE PRODUCT DSEIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE
September 03.2010-REV.00
PAGE . 1
2N7002FN3
ELECTRICAL CHARACTERISTICS
PAR AME T E R
S t a tic
D r a i n- S o urc e B re a k d o wn Vo lta g e
Ga te Thr e s ho ld Vo lta g e
D r a i n- S o urc e On-S ta te Re s i s ta nc e
D r a i n- S o urc e On-S ta te Re s i s ta nc e
Ze ro Ga te Vo lta g e D ra i n C ur re nt
Ga te B o d y L e a k a g e
F o rwa r d Tr a ns c o nd uc ta nc e
D y n a m ic
To ta l Ga te C ha r g e
Ga te -S o urc e C ha rg e
Ga te -D ra i n C ha r g e
Turn-On D e la y Ti m e
Turn-Off D e la y Ti m e
Inp ut C a p a c i ta nc e
Outp ut C a p a c i ta nc e
Re ve rs e Tra ns fe r C a p a c i ta nc e
S o u rc e - D r a in D io d e
M a x.D i o d e F o r wa r d C ur re nt
D i o d e F o re a rd Vo lta g e
I
S
S YMB OL
T E S T C ON D IT ION
MIN .
T YP.
MAX .
U N IT S
B V
DSS
V
GS (
th
)
R
D S ( O N)
R
D S ( O N)
I
I
V
GS
=0 V, I
D
=10mA
60
1
-
-
-
-
100
-
-
-
-
-
-
-
-
2 .5
7 .5
V
V
V
D S
=V
G S
, I
D
= 2 5 0 mA
V
GS
=4 .5 V, I
V
GS
=1 0 V, I
D
= 5 0 mA
W
D
=5 0 0 m A
5
1
+100
-
mA
nA
mS
DSS
V
D S
=6 0 V,V
G S
= 0 V
V
GS
=+ 2 0 V,V
D S
= 0 V
V
D S
=1 5 V, I
D
=2 5 0 m A
GS S
g
FS
Q
G
Q
GS
Q
GD
V
D S
=1 5 V, I
D
=5 0 0 m A ,
-
V
GS
= 4 . 5 V
-
-
-
V
D D
= 1 0 V,R
L
= 2 0 W
I
D
= 5 0 0 m A ,V
GE N
= 1 0 V,R
G
= 1 0 W
-
-
V
D S
=2 5 V, V
G
s = 0 V, f= 1 .0 M Hz
-
-
0 .6
0 .1
0 .0 8
9
21
-
-
-
0 .7
-
-
15
ns
26
50
25
5
pF
nC
TO N
t
OFF
C
IS S
C
OS S
C
RS S
-
I
S
= 2 5 0 mA ,V
GS
= 0 V
-
-
-
0 .9 3
11 5
1 .2
mA
V
SD
Switching
Test Circuit
V
IN
V
DD
R
L
V
OUT
Gate Charge
Test Circuit
V
GS
V
DD
R
L
R
G
1mA
R
G
September 03.2010-REV.00
PAGE . 2
2N7002FN3
MOUNTING PAD LAYOUT
DFN 3L
0.043
(1.10)
0.017
(0.42)
0.010
(0.26)
0.02 8
(0.70)
0.004
(0.10)
0.02 7
(0.68)
ORDER INFORMATION
• Packing information
T/R - 8K per 7" plastic Reel
LEGAL STATEMENT
Copyright PanJit International, Inc 2010
The information presented in this document is believed to be accurate and reliable. The specifications and information herein
are subject to change without notice. Pan Jit makes no warranty, representation or guarantee regarding the suitability of its
products for any particular purpose. Pan Jit products are not authorized for use in life support devices or systems. Pan Jit
does not convey any license under its patent rights or rights of others.
September 03.2010-REV.00
0.010
(0.25)
0.024
(0.60)
PAGE . 3
电子竞赛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
