HIGH-SPEED 2.5V
16/8K X 9 DUAL-PORT
STATIC RAM
.eatures
x
x
PRELIMINARY
IDT70T16/5L
x
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial:20/25ns (max.)
– Industrial: 25ns (max.)
Low-power operation
– IDT70T16/5L
Active: 200mW (typ.)
Standby: 600
µ
W (typ.)
x
IDT70T16/5 easily expands data bus width to 18 bits or
more using the Master/Slave select when cascading more
than one device
x
x
x
x
x
x
x
x
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 2.5V (±100mV) power supply
Available in an 80-pin TQFP and 100-pin
fpBGA
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
.unctional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
8L
I/O
Control
BUSY
L
(2,3)
I/O
0R
-I/O
8R
I/O
Control
BUSY
R
(2,3)
Address
Decoder
14
A
13L
(1)
A
0L
MEMORY
ARRAY
14
Address
Decoder
A
13R
(1)
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(3)
INT
L
NOTES:
1. A
13
is a NC for IDT70T15.
2. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
3.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull drivers.
M/S
SEM
R
(3)
INT
R
5663 drw 01
AUGUST 2002
1
©2002 Integrated Device Technology, Inc.
DSC 5663/1
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Description
The IDT70T16/5 is a high-speed 16/8K x 9 Dual-Port Static RAM.
The IDT70T16/5 is designed to be used as stand-alone Dual-Port RAMs
or as a combination MASTER/SLAVE Dual-Port RAM for 18-bit-or-more
wider systems. Using the IDT MASTER/SLAVE Dual-Port RAM ap-
proach in 18-bit or wider memory system applications results in full-speed,
error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by
CE
permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 200mW of power.
The IDT70T16/5 is packaged in an 80-pinTQFP (Thin Quad Flatpack)
and a 100-pin
fpBGA
(fine pitch Ball Grid array) .
Pin Configurations
(1,2,3,4)
I/O
1L
I/O
0L
I/O
8L
OE
L
R/W
L
SEM
L
CE
L
NC
V
DD
A
12L
A
11L
A
10L
07/11/02
NC
A
13L
(1)
A
7L
A
6L
A
9L
A
8L
INDEX
79
78
77
76
70
69
72
71
66
65
64
63
62
80
75
68
67
61
74
73
NC
NC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
NC
I/O
2L
I/O
3L
I/O
4L
I/O
5L
V
SS
I/O
6L
I/O
7L
V
DD
NC
V
SS
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I/O
6R
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
NC
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
V
SS
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
NC
NC
,
IDT70T16/5PF
PN80-1
(5)
80-Pin TQFP
Top View
(6)
21
27
28
30
31
33
34
37
38
26
35
24
25
29
32
36
39
40
NC
20
22
23
42
41
I/O
7R
I/O
8R
OE
R
A
13R
(1)
V
SS
NC
NC
R/W
R
SEM
R
CE
R
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
NOTES:
1. A
13
is a NC for IDT70T15.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 1.18 in x 1.18 in x 0.16 in.
5. This package code is used to reference the package diagram.
6. This text does not imply orientation of Part-marking.
2
6.42
A
5R
NC
5663 drw 02
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Pin Configurations (con't.)
(1,2,3,4)
IDT70T16/5BF
BF100
(5)
100-Pin fpBGA
Top View
(6)
08/14/02
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A
6R
B1
A
9R
B2
A
12R
B3
NC
B4
V
SS
B5
V
SS
B6
NC
B7
R/W
R
B8
NC
B9
I/O
7R
B10
NC
C1
NC
C2
A
8R
C3
A
10R
C4
NC
C5
NC
C6
A
13R
(1)
C7
OE
R
C8
I/O
8R
C9
I/O
6R
C10
A
3R
D1
A
4R
D2
A
5R
D3
A
7R
D4
NC
D5
NC
D6
CE
R
D7
NC
D8
NC
D9
I/O
3R
D10
A
1R
E1
INT
R
E2
A
2R
E3
NC
E4
A
11R
E5
NC
E6
SEM
R
E7
NC
E8
I/O
5R
I/O
1R
E9
E10
M/S
BUSY
R
F1
F2
A
0R
F3
A
1L
F4
V
SS
F5
V
SS
F6
I/O
4R
F7
I/O
2R
F8
I/O
0R
F9
V
DD
F10
V
SS
G1
BUSY
L
G2
A
0L
G3
NC
G4
V
DD
G5
V
SS
G6
V
DD
G7
I/O
5L
G8
I/O
6L
G9
I/O
7L
G10
INT
L
H1
A
3L
H2
A
6L
H3
NC
H4
NC
H5
SEM
L
H6
NC
H7
I/O
3L
H8
V
SS
H9
I/O
4L
H10
,
A
2L
J1
A
5L
J2
A
10L
J3
NC
J4
NC
J5
CE
L
I/O
8L
NC
NC
J9
I/O
2L
J10
A
4L
K1
A
8L
K2
A
11L
K3
NC
K4
NC
K5
J8
J6
J7
A
13L
(1)
R/W
L
NC
K6
K7
K8
V
SS
K9
I/O
1L
K10
A
7L
A
9L
A
12L
NC
V
DD
V
DD
NC
NC
OE
L
I/O
0L
5 6 63 d rw 0 3
NOTES:
1. A
13
is a NC for IDT70T15.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground.
4. BF-100 package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.42
3
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
L
R/W
L
OE
L
A
0L
- A
13L
(1)
I/O
0L
- I/O
8L
SEM
L
INT
L
BUSY
L
CE
R
R/W
R
OE
R
A
0R
- A
13R
(1)
I/O
0R
- I/O
8R
SEM
R
INT
R
BUSY
R
M/S
V
DD
V
SS
NOTE:
1. A
13
is a NC for IDT70T15.
Right Port
Names
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power (2.5V)
Ground (0V)
5663 tbl 01
Truth Table I: Non-Contention Read/Write Control
Inputs
(1)
CE
H
L
L
X
R/W
X
L
H
X
OE
X
X
L
H
SEM
H
H
H
X
Outputs
I/O
0-8
High-Z
DATA
IN
DATA
OUT
High-Z
Deselcted: Power-Down
Write to Memory
Read Memory
Outputs Disabled
5663 tbl 02
Mode
NOTE:
1.
Condition: A
0L
— A
13L
≠
A
0R
— A
13R
Truth Table II: Semaphore Read/Write Control
(1)
Inputs
CE
H
H
L
R/W
H
↑
X
OE
L
X
X
SEM
L
L
L
Outputs
I/O
0-8
DATA
OUT
DATA
IN
____
Mode
Read Semaphore Flag Data Out (I/O
0
- I/O
8
)
Write I/O
0
into Semaphore Flag
Not Allowed
5663 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from all I/O
s
(I/O
0
-I/O
8
). These eight semaphores are addressed by A
0
- A
2.
4
6.42
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
(1)
S ym b o l
V
TERM
(2 )
T
BIAS
T
STG
T
JN
I
OUT
(3 )
Ratin g
Te rm in al V o ltag e
w ith R e s p e c t to G N D
Te m p e ra tu re U n d e r B ia s
S to ra g e Te m p e ra ture
J u n c tio n Te m p e rature
D C O u tp u t C urre nt
Co m m ercial
& In du strial
-0.5 to + 3 .6
-55 to + 1 25
-65 to + 1 50
+ 15 0
50
Un it
V
o
Maximum Operating
Temperature and Supply Voltage
(1)
Grade
Co m m e rc ial
Ind ustrial
Am bient
Tem perature
0
O
C to + 70
O
C
-40
O
C to + 85
O
C
GND
0V
0V
V
DD
2.5V
+
100m V
2.5V
+
100m V
5663 tbl 05
C
C
C
o
o
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
mA
5 6 63 tb l 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. V
TERM
must not exceed V
DD
+ 0.3V.
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.
Recommended DC Operating
Conditions
S y m b ol
V
DD
V
SS
V
IH
V
IL
P aram eter
S u p p ly Vo lta g e
G ro u n d
In p u t H ig h Vo lta g e
In p u t L o w V o lta g e
M in.
2.4
0
1.7
-0 .3
(1 )
Typ.
2.5
0
_ __ _
M ax.
2.6
0
V
D D
+ 0 . 3
(2 )
0.7
Un it
V
V
V
V
5 6 63 tb l 06
_ __ _
Capacitance
(1)
(T
A
= +25°C, f = 1.0MHz)
Sym bol
C
IN
C
O UT
Param eter
Inp ut Cap acitanc e
Outp ut Cap ac itance
Conditions
(2)
V
IN
= 3d V
V
O UT
= 3d V
M ax.
9
10
Unit
pF
pF
5663 tbl 07
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed V
DD
+ 0.3V.
NOTES:
1. This parameter is determined by device characteristics but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V .
DC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(V
DD
= 2.5V ± 100mV)
70T 16/ 5L
S y m bo l
|I
LI
|
|I
LO
|
V
OL
V
OH
P ara m eter
Inp ut Le ak ag e C urre nt
(1 )
T est C on d itio ns
V
DD
= 2.6V, V
IN
= 0V to V
DD
CE
= V
IH
, V
O UT
= 0V to V
DD
I
O L
= + 2m A
I
OH
= -2m A
M in.
__ _
__ _
__ _
M a x.
5
5
0. 4
__ _
Un it
µA
µA
V
V
5663 tb l 0 8
O utp ut L e ak ag e C urre nt
O utp ut L o w Vo ltag e
O utp ut H ig h Vo ltag e
2. 0
NOTE:
1. At V
DD
< 2.0V, Input leakages are undefined.
6.42
5
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