IDT74LVC161A
3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS PRESETTABLE
SYNCHRONOUS 4-BIT BINARY
COUNTER WITH ASYNCHRONOUS
RESET, 5 VOLT TOLERANT I/O
FEATURES:
–
–
–
–
–
–
–
–
–
–
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
1.27mm pitch SOIC, 0.635mm pitch QSOP,
0.65mm pitch SSOP, 0.65mm pitch TSSOP packages
Extended commercial range of – 40°C to +85°C
V
CC
= 3.3V ±0.3V, Normal Range
V
CC
= 2.3V to 3.6V, Extended Range
CMOS power levels (0.4µ W typ. static)
Rail-to-Rail output swing for increased noise margin
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
IDT74LVC161A
counting. Synchronous operation is provided by having all flip-flops clocked
simultaniously on the positive-going edge of the clock (CP). Outputs (Q
0
to
Q
3
) of the counters may be preset to a high or low level. A low level at the
parallel enable input (PE) disables the counting action and causes the data
at inputs (D
0
to D
3
) to be loaded into the counter on the positive-going edge
of the clock (provided that the set-up and hold time requirements for
PE
are
met). Preset takes place regardless of the levels at the count enable inputs
(CEP and CET). A low level at the master reset input (MR) sets all four outputs
of the flip-flops (Q
0
to Q
3
) to low level regardless of the levels at CP,
PE,
CET,
and CEP inputs (thus providing an asynchronous clear function).
The look-ahead carry simplifies serial cascading of the counters. Both
count enable inputs (CEP and CET) must be high to count. The CET input
is fed forward to enable the terminal count output (TC). The TC output thus
enabled will produce a high output pulse of a duration approximately equal
to a high level output of Q
0
. This pulse can be used to enable the next
cascaded stage. The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP to CP set-up time,
according to the following formula:
f
max
=
1
tp
(max)
(CP to TC) + t
su
(CEP to CP)
Drive Features for LVC161A:
– High Output Drivers: ±24mA
– Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DESCRIPTION:
The LVC161A is a high-performance, low-power, low-voltage, Si-gate
CMOS device, superior to most advanced CMOS-compatible TTL families.
The LVC161A is a presettable synchronous binary counter which
features an internal look-ahead carry and can be used for high-speed
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
FUNCTIONAL DIAGRAM
3
4
5
6
STATE DIAGRAM
0
1
2
3
4
D
0
9
D
1
D
2
D
3
PE
PARALLEL LO AD
CIRCUITRY
CET
15
5
10
TC
7
15
CEP
14
6
2
CP
BINARY CO UNTER
13
7
1
MR
12
Q
0
Q
1
Q
2
Q
3
14
13
12
11
11
10
9
8
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-5156/-
IDT74LVC161A
3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
EXTENDED COMMERCIAL TEMPERATURE RANGE
TYPICAL TIMING SEQUENCE
MR
PE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through
each V
CC
or GND
LVC QUAD Link
Max.
– 0.5 to +6.5
– 65 to +150
– 50 to +50
– 50
±100
Unit
V
°C
mA
mA
mA
D0
D1
D2
D3
CP
CEP
CET
Q0
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Q1
Q2
Q3
CAPACITANCE
(T
A
= +25°C, f = 1.0MH
Z
)
Symbol
12
RESET PRESET
13
14
15
0
COUNT
1
2
INHIBIT
TC
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
5.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
C
IN
C
OUT
C
I/O
PIN CONFIGURATION
MR
CP
D
0
D
1
D
2
D
3
CEP
GND
1
2
3
4
5
6
7
8
16
15
14
SO16-7
13
SO16-8
SO16-9
12
SO16-10
LVC QUAD Link
NOTE:
1. As applicable to the device type.
V
CC
TC
Q
0
Q
1
Q
2
Q
3
CET
PE
PIN DESCRIPTION
Pin Names
MR
CP
Dx
CEP
GND
PE
CET
Qx
TC
Vcc
Description
Asynchronous Master Reset (Active LOW)
Clock Input (LOW-to-HIGH, Edge-Triggered)
Data Inputs
Count Enable Inputs
Ground (0V)
Parallel Enable Input (Active LOW)
Count Enable Carry Input
Flip-Flop Outputs
Terminal Count Output
Positive Supply Voltage
11
10
9
SOIC/ SSOP/ TSSOP/ QSOP
TOP VIEW
3
IDT74LVC161A
3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
EXTENDED COMMERCIAL TEMPERATURE RANGE
FUNCTION TABLE
OPERATING
MODES
Reset (clear)
Parallel load
Count
Hold
(do nothing)
MR
L
H
H
H
H
H
(1)
INPUTS
CP
X
↑
↑
↑
X
X
CEP
X
X
X
h
l
X
CET
X
X
X
h
X
l
PE
X
l
l
h
h
h
Dx
X
l
h
X
X
X
Qx
L
L
H
count
Q
0
Q
0
OUTPUTS
TC
L
L
*
*
*
L
NOTE:
1. H = HIGH Voltage Level
h = HIGH Voltage level one setup time prior to the LOW-to-HIGH clock transition.
L = LOW Voltage Level
l = LOW Voltage level one setup time prior to the LOW-to-HIGH clock transition.
Q
0
= Indicates the state of the referenced output one set up time prior to the LOW-to-HIGH clock transition.
X = Don’t care
* = The TC output is HIGH when CET is HIGH and the counter is at Terminal Count (HHHH).
↑
= LOW-to-HIGH clock transition
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= – 40°c to +85°c
Symbol
V
IH(2)
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
OFF
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input Leakage Current
High Impedance Output Current
(3-State Output pins)
Input/Output Power Off Leakage
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 0V, V
IN
or V
O
≤5.5V
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
—
—
—
—
—
– 0.7
100
—
±50
– 1.2
—
10
µA
V
mV
µA
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= 0 to 5.5V
V
O
= 0 to 5.5V
Min.
1.7
2
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
Max.
—
—
0.7
0.8
±5
±10
µA
µA
V
Unit
V
Quiescent Power Supply
Current Variation
One input at V
CC
– 0.6V
other inputs at V
CC
or GND
—
—
500
µA
NOTES:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
2. Clock Pin (CP) requires a minimum
V
IH
of 2.5V.
c
1998 Integrated Device Technology, Inc.
4
DSC-123456
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