Datasheet> 器件分类 > 无线/射频/通信> 电信电路> PT7D6555J

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PT7D6555J: 产品描述PCM Transceiver, 1-Func, PQCC44, PLASTIC, LCC-44; 产品类别无线/射频/通信电信电路; 文件大小489KB，共56页; 制造商Pericom Semiconductor Corporation (Diodes Incorporated); 官网地址https://www.diodes.com/

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PT7D6555J概述

PCM Transceiver, 1-Func, PQCC44, PLASTIC, LCC-44

PT7D6555J规格参数

参数名称	属性值
是否无铅	含铅
是否Rohs认证	不符合
厂商名称	Pericom Semiconductor Corporation (Diodes Incorporated)
零件包装代码	LCC
包装说明	QCCJ,
针数	44
Reach Compliance Code	compliant
ECCN代码	EAR99
JESD-30 代码	S-PQCC-J44
JESD-609代码	e0
长度	16.61 mm
湿度敏感等级	3
功能数量	1
端子数量	44
最高工作温度	85 °C
最低工作温度	-40 °C
封装主体材料	PLASTIC/EPOXY
封装代码	QCCJ
封装形状	SQUARE
封装形式	CHIP CARRIER
峰值回流温度（摄氏度）	240
认证状态	Not Qualified
座面最大高度	4.64 mm
标称供电电压	5 V
表面贴装	YES
电信集成电路类型	PCM TRANSCEIVER
温度等级	INDUSTRIAL
端子面层	Tin/Lead (Sn/Pb)
端子形式	J BEND
端子节距	1.27 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	16.61 mm

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Preliminary Data Sheet

PT7D6555

Extended PCM Interface Controller

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Features

Switching Feature

• Board Controller for up to 32 ISDN or 64 analog

subscribers

• Non-blocking switch for 128 channels

• Switching of 16-, 32-, or 64-kbit/s channels

• Two consecutive 64-kbit/s channels can be

switched as a single 128-kbit/s channel

• Freely programmable time slot assignment for all

subscribers

• Two serial interfaces (PCM and CFI) programmable

over a wide data range (128 - 8192 kbit/s)

• Data rates of PCM and Configurable interface

independent from each other (data rate adaptation)

• PCM-interface

- Tristate control signals for external drivers

- Programmable clock shift

- Single or double data clock

• Configurable interface

- Configurable for IOM-, SLD- and PCM-

applications

- High degree of flexibility for datastream adaptation

- Programmable clock shift

- Single or double data clock

• Synchronous

µP-access

to two selected channels

Introduction

The PT7D6555 is a highly integrated controller circuit

optimized for analog and ISDN line card and central

switch applications. It provides the circuitry necessary

to manage up to 32 digital (ISDN or proprietary) or

64 analog subscribers.

PT7D6555 is dedicated to switch PCM data between

two serial interfaces, the system interface (PCM

interface) and the configurable interface (CFI). The

device performs non-blocking time and space

switching for up to 128 channels. Since the system

cost of the PT7D6555 is divided by the number of

lines it controls, an highly economical implementation

of digital or analog subscriber lines can be performed.

Applications

•

Digital line cards with different architectures,

Central control units of key systems,

Analog line cards,

Concentrators.

Ordering Information

Pa r t Nu m b er

PT7D6555J

Pa ck a ge

44 - Pin PLCC

Handling of Layer-1 Functions

• Change detection for C/I-channel (IOM-configura-

tion) or feature control (SLD-configuration)

• Double last-look logic for C/I-channel (IOM-2

analog configuration)

• Additional last-look logic for feature control (SLD-

configuration)

• Buffered monitor (IOM-configuration) or

signalling channel (SLD-configuration)

Bus Interface

• Intel or Motorola type

µP-interface

• 8-bit demultiplexed bus interface

• FIFO-access interrupt

PT0105(08/02)

Ver:0

Preliminary Data Sheet

PT7D6555

Extended PCM Interface Controller

Contents

Features ....................................................................................................................................................... 1

Applications ................................................................................................................................................ 1

Introduction ................................................................................................................................................. 1

Ordering Information .................................................................................................................................. 1

Block Diagram ............................................................................................................................................ 2

Pin Information ........................................................................................................................................... 5

Pin Configuration ................................................................................................................................. 5

Pin Description ..................................................................................................................................... 6

Typical Applications .................................................................................................................................... 8

Digital Line Card .................................................................................................................................. 8

Analog Line Card ............................................................................................................................... 10

Packet Handlers .................................................................................................................................. 11

Functional Description .............................................................................................................................. 14

Bus Interface ....................................................................................................................................... 14

PCM Interface .................................................................................................................................... 14

Configurable Interface ........................................................................................................................ 14

Memory Structure and Switching ....................................................................................................... 15

Pre-processed Channels, Layer-1 Support .......................................................................................... 16

Special Functions ................................................................................................................................ 16

Operational Description ............................................................................................................................ 17

Microprocessor Interface Operation.................................................................................................... 17

Clocking ............................................................................................................................................. 17

Reset ................................................................................................................................................... 17

Operation ............................................................................................................................................ 18

Initialization Procedure ....................................................................................................................... 23

(To be Cont’d)

PT0105(08/02)

Ver:0

Preliminary Data Sheet

PT7D6555

Extended PCM Interface Controller

Register ..................................................................................................................................................... 25

Address Assignment ........................................................................................................................... 25

PCM Interface Registers ..................................................................................................................... 26

PCM-Mode Register (PMOD) ....................................................................................................................................26

Bit Number per PCM-Frame (PBNR) .........................................................................................................................27

PCM-Offset Downstream Register (POFD) .................................................................................................................27

PCM-Offset Upstream Register (POFU) ......................................................................................................................27

PCM-Clock Shift Register (PCSR) .............................................................................................................................28

PCM-Input Comparison Mismatch (PICM) ............................................................................................................... 28

Configurable Interface Registers ......................................................................................................... 29

Configurable Interface Mode Register 1 (CMD1) .....................................................................................................29

Configurable Interface Mode Register 2 (CMD2) .....................................................................................................30

Configurable Interface Bit Number Register (CBNR) ...............................................................................................32

Configurable Interface Time Slot Adjustment Register (CTAR) ...............................................................................32

Configurable Interface Bit Shift Register (CBSR) .....................................................................................................32

Configurable Interface Subchannel Register (CSCR) ................................................................................................33

Memory Access Registers ................................................................................................................... 34

Memory Access Control Register (MACR) ................................................................................................................34

Memory Access Address Register (MAAR) ................................................................................................................36

Memory Access Data Register (MADR) ..................................................................................................................... 36

Synchronous Transfer Registers ......................................................................................................... 37

Synchronous Transfer Data Register A (STDA) ..........................................................................................................37

Synchronous Transfer Data Register B (STDB) ......................................................................................................... 37

Synchronous Transfer Receive Address Register A (SARA) ......................................................................................37

Synchronous Transfer Receive Address Register B (SARB) ......................................................................................37

Synchronous Transfer Transmit Address Register A (SAXA) .....................................................................................38

Synchronous Transfer Transmit Address Register B (SAXB) .....................................................................................38

Synchronous Transfer Control Register (STCR) ........................................................................................................39

Monitor/Feature Control Registers ...................................................................................................... 39

MF-Channel Active Indication Register (MFAIR) .....................................................................................................39

Monitor/Feature Control Channel FIFO (MFFIFO) ................................................................................................... 40

MF-Channel Subscriber Address Register (MFSAR) .................................................................................................40

Status/Control Registers...................................................................................................................... 41

Signaling FIFO (CIFIFO) ............................................................................................................................................41

Timer Register (TIMR) ...............................................................................................................................................41

Status Register (STAR) ...............................................................................................................................................42

Command Register (CMDR) ......................................................................................................................................43

Mask Register (MASK) ..............................................................................................................................................44

Operation Mode Register (OMDR) ............................................................................................................................45

Version Number Status Register (VNSR) ...................................................................................................................46

Detailed Specification ............................................................................................................................... 47

Absolute Maximum Ratings ............................................................................................................... 47

Recommended Operating Conditions ................................................................................................. 47

DC Electrical, Power Supply and Capacitance Characteristics........................................................... 48

AC Electrical Characteristics .............................................................................................................. 48

Notes ......................................................................................................................................................... 55

PT0105(08/02)

Ver:0

PT7D6555J

PT7D6555J概述

PT7D6555J规格参数

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