Data Sheet
PT7A8980/8980L Digital Switch
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Features
• Compatible with ST-BUS
• 8 full duplex, 32-channel time-division
multiplexed (TDM) data streams
• 256 ports non-blocking switch
• Power supply: 5V (8980) and 3.3V (8980L)
• Microprocessor interface
• Tri-state serial output port
Description
PT7A8980/8980L is designed to handle data in ST-BUS
format. It interfaces with a microprocessor to switch
PCM-encoded voice or data in application areas such as
modern digital exchange, PBX and Central Office.
PT7A8980/8980L can simultaneously connect up to 256
channels of 64 kbit/s each. It has 8 data stream inputs
and 8 data stream outputs. Each data stream consists of
32 multiplexed 64 kbit/s channels which is compatible to
2048 kbit/s ST-BUS format.
Its microprocessor interfaces not only allow access to
the internal registers and memory, but also provide means
to read from the input channels or to write to the output
channels.
Pa ck a ge
40- Pin DIP
44- Pin PLCC
44- Pin PLCC
Lead free 44- Pin PLCC
Lead free 44- Pin PLCC
Applications
• PBX
• Central office
• Access Switch
Ordering Information
Pa r t Numbe r
PT7A8980P
PT7A8980J
PT7A8980LJ
PT7A8980JE
PT7A8980LJE
PT0011(12/05)
1
Ver:5
Data Sheet
PT7A8980/8980L Digital Switch
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Table of Contents
Contents
Page
Features ............................................................................................................................................ 1
Applications ...................................................................................................................................... 1
Description ........................................................................................................................................ 1
Ordering Information ........................................................................................................................ 1
Block Diagram .................................................................................................................................. 3
Pin Information ................................................................................................................................. 4
Pin Assignment ......................................................................................................................... 4
Pin Configuration ...................................................................................................................... 4
Pin Description ......................................................................................................................... 5
Functional Description ....................................................................................................................... 6
Input and Output Control ......................................................................................................... 6
Microprocessor Interface and Address Selection ...................................................................... 6
ST-BUS Timing Reference ....................................................................................................... 7
Control Register ....................................................................................................................... 7
Normal Mode .......................................................................................................................... 8
Message Mode ........................................................................................................................ 8
ST-BUS Output High Impedance ............................................................................................. 8
CSTo Output ........................................................................................................................... 8
Detailed Specifications ..................................................................................................................... 10
Absolute Maximum Ratings .................................................................................................. 10
Recommended Operating Conditions ...................................................................................... 10
DC Electrical, Power Supply and Capacitance Characteristics ................................................ 11
AC Electrical Characteristics ................................................................................................. 12
Mechanical Information ......................................................................................................... 17
Notes .............................................................................................................................................. 19
PT0011(12/05)
2
Ver:5
Data Sheet
PT7A8980/8980L Digital Switch
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Block Diagram
Figure.1 Block Diagram
ODE
STi0-STi7
Serial
To
Parallel
Converter
Data
Memory
Output
MUX
Parallel
To
Serial
Converter
STo0-STo7
Control Register
Connection
Memory
Microprocessor Interface
Frame
Counter
DS CS R/W A0-A5 DTA D0-D7
CSTo
C4i
F0i
PT0011(12/05)
3
Ver:5
Data Sheet
PT7A8980/8980L Digital Switch
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Pin Information
Pin Assignment
Table1. Pin Assignment
G r ou p
Chip Clock
Power & Ground
Microprocessor Interface
I/O Interface
Symb ol
C4i, F0i
GND, Vcc
CS, DS, DTA, ODE, CSTo, R/W,
A0~A5
D0-D7, STi0-STi7, STo0-STo7
F u n ct ion
Clock
Power
Control or Data
Data
Pin Configuration
Figure 2. Pin Configuration
DTA
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
Vcc
F0i
C4i
A0
A1
A2
A3
A4
A5
DS
R/W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40-Pin
DIP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CSTo
ODE
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
GND
D0
D1
D2
D3
D4
D5
D6
D7
CS
6
5
4
3
2
1
44
43
42
41
40
NC
STi2
STi1
STi0
DTA
CSTo
ODE
STo0
STo1
STo2
NC
Top View
PT0011(12/05)
NC
A3
A4
A5
DS
R/W
CS
D7
D6
D5
NC
18
19
20
21
22
23
24
25
26
27
28
STi3
STi4
STi5
STi6
STi7
V
CC
F0i
C4i
A0
A1
A2
7
8
9
10
11
12
13
14
15
16
17
44-Pin
PLCC
39
38
37
36
35
34
33
32
31
30
29
STo3
STo4
STo5
STo6
STo7
GND
D0
D1
D2
D3
D4
4
Ver:5
Data Sheet
PT7A8980/8980L Digital Switch
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Pin Description
Table 2. Pin Description
P in
Na me
P DI P
1
2-4
5-9
10
PLCC
2
3-5
7-11
12
DTA
STi0-STi2
STi3-STi7
Vcc
O
I
I
Power
Da t a Ack n owled gemen t (O p en Dr a in O u t p u t ). This pin, when pulled low,
acknowledges the microprocessor that the chip has processed the data. Using
1k
Ω
1/4W pull-up resistor is recommended.
0~2 ST-BUS d a t a st r ea m in p u t . Input pin of 2048 kbit/s ST-BUS data stream.
3~7 ST-BUS d a t a st r ea m in p u t . Input pin of 2048kbit/s ST-BUS data stream.
Power su p p ly.
F r a m in g sign a l, a ct ive low. It is the input pin that provides the frame
synchronization pulse for 2048kbit/s ST-BUS data stream. A low level on this
input pin causes the internal counter to reset on the next negative transition
of C4i signal.
4.096 MH z clock . The bit cell boundaries of operating ST-BUS data stream
are aligned with every other falling edges of this clock.
Ad d r ess lin e 0~2. Address pins of the control interface.
Ad d r ess lin e 3~5. Address pins of the control interface.
Da t a St r ob e. Data strobe pin of the control interface, active high.
R ea d or Wr it e Sign a l. The read or write signal pin of the control interface,
high level for read, low level for write.
C h ip select sign a l. Chip selects signal pin of the control interface, active low.
Da t a Bu ses 5~7. Bi-directional data pins of the control interface.
Da t a Bu ses 0~4. Bi-drectional data pins of the control interface.
C on n ect ed t o gr ou n d .
ST-BUS Da t a St r ea m O u t p u t 3~7. Output pins of 2048 kbit/s ST-BUS data
stream.
ST-BUS Da t a St r ea m O u t p u t 0~2. Output pins of 2048 kbit/s ST-BUS data
stream.
O u t p u t Dr ive E n a b le. If its input is held high, STo0~STo7 outputs behave
normally. If its input is held low, STo0~STo7 outputs are forced into high
impedance state. [Note]: Even when ODE is high level, certain channels of
STo0~STo7 output stream can also enter into high impedance state under
software control.
Su p p lemen t ST-BUS O u t p u t . This pin also outputs serial data stream of ST-
BUS format. Each frame has 256 bits, containing the values of bit 1 in all
Connection Memory High (256 locations).
Typ e
Descr ip t ion
11
13
F0i
I
12
13-15
16-18
19
20
21
22-24
25-29
30
31-35
36-38
14
15-17
19-21
22
23
24
25-27
29-33
34
35-39
41-43
C4i
A0-A2
A3-A5
DS
R/W
CS
D5-D7
D0-D4
GND
STo3-STo7
STo0-STo2
I
I
I
I
I
I
I/O
I/O
Power
O
O
39
44
ODE
I
40
1
CSTo
O
PT0011(12/05)
5
Ver:5
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