IDT54/74FCT16260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS
12-BIT TRI-PORT
BUS EXCHANGER
FEATURES:
−
−
−
−
−
−
−
−
−
−
−
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical t
SK
(o) (Output Skew) < 250ps
Low input and output leakage
≤1µ
A (max.)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 5V ±10%
High drive outputs (-32mA I
OH
, 64mA I
OL
)
Power off disable outputs permit “live insertion”
Typical V
OLP
(Output Ground Bounce) < 1.0V at V
CC
= 5V, T
A
=
25°C
Power off disable outputs permit “live insertion”
Available in the following packages:
•
Industrial: SSOP, TSSOP, TVSOP
•
Military: CERPACK
IDT54/74FCT16260AT/CT/ET
DESCRIPTION:
The FCT16260T Tri-Port Bus Exchangers are high-speed 12-bit
latched bus multiplexers/transceivers for use in high-speed microprocessor
applications. These Bus Exchangers support memory interleaving with
latched outputs on the B ports and address multiplexing with latched inputs
on the B ports.
The Tri-Port Bus Exchanger has three 12-bit ports. Data may be
transferred between the A port and either/both of the B ports. The latch
enable (LE1B, LE2B, LEA1B and LEA2B) inputs control data storage.
When a latch-enable input is high, the latch is transparent. When a latch-
enable input is low, the data at the input is latched and remains latched until
the latch enable input is returned high. Independent output enables (OE1B
and
OE2B)
allow reading from one port while writing to the other port.
The FCT16260T is ideally suited for driving high capacitance loads and
low impedance backplanes. The output buffers are designed with power
off disable capability to allow "live insertion" of boards when used as
backplane drivers.
FUNCTIONAL BLOCK DIAGRAM
29
OE1B
30
LEA1B
A-1B
LATCH
12
1B
1:12
2
LE1B
12
28
1
12
1B-A
LATCH
12
SEL
OEA
A
1:12
12
M1
U
X 0
12
12
27
LE2B
2B-A
LATCH
12
55
LEA2B
56
A-2B
LATCH
12
2B
1:12
OE2B
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
c
1999 Integrated Device Technology, Inc.
JUNE 2000
DSC-5431/-
IDT54/74FCT16260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
OEA
LE1B
2B
3
GND
2B
2
2B
1
V
CC
A
1
A
2
A
3
GND
A
4
A
5
A
6
A
7
A
8
A
9
GND
A
10
A
11
A
12
V
CC
1B
1
1B
2
GND
1B
3
LE2B
SEL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SO56-1
SO56-2
SO56-3
E56-1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OE2B
LEA2B
2B
4
GND
2B
5
2B
6
V
CC
2B
7
2B
8
2B
9
GND
2B
10
2B
11
2B
12
1B
12
1B
11
1B
10
GND
1B
9
1B
8
1B
7
V
CC
1B
6
1B
5
GND
1B
4
LEA1B
OE1B
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
5v16-link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
Max.
6
8
Unit
pF
pF
5v16-link
NOTE:
1. This parameter is measured at characterization but not tested.
SSOP/ TSSOP/ TVSOP/ CERPACK
TOP VIEW
2
IDT54/74FCT16260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION
Signal
A
(1:12)
1B
(1:12)
2B
(1:12
)
LEA1B
LEA2B
LE1B
LE2B
SEL
OEA
OE1B
OE2B
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
Description
Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.
Bidirectional Data Port 1B. Connected to the even path or even bank of memory.
Bidirectional Data Port 2B. Connected to the odd path or odd bank of memory.
Latch Enable Input for A-1B Latch. The Latch is open when LEA1B is HIGH. Data from the A-port is latched on the HIGH to LOW transition
of LEA1B.
Latch Enable Input for A-2B Latch. The Latch is open when LEA2B is HIGH. Data from the A-Port is latched on the HIGH to LOW transition
of LEA2B.
Latch Enable Input for the 1B-A Latch. The Latch is open when LE1B is HIGH. Data from the 1B port is latched on the HIGH to LOW transition
of LE1B.
Latch Enable Input for the 2B-A Latch. The Latch is open when LE2B is HIGH. Data from the 2B port is latched on the HIGH to LOW transition
of LE2B.
1B or 2B Path Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL enables data transfer from 2B Port
to A Port.
Output Enable for A Port (Active LOW).
Output Enable for 1B Port (Active LOW).
Output Enable for 2B Port (Active LOW).
FUNCTION TABLES
(1)
1B
H
L
X
X
X
X
X
2B
X
X
X
H
L
X
X
Inputs
SEL
LE1B
H
H
H
L
L
L
X
H
H
L
X
X
X
X
LE2B
X
X
X
H
H
L
X
OEA
L
L
L
L
L
L
H
Output
A
H
L
A
(1)
H
L
A
(1)
Z
Inputs
A
H
L
H
L
H
L
X
X
X
X
X
LEA1B LEA2B
H
H
H
H
L
L
L
X
X
X
X
H
H
L
L
H
H
L
X
X
X
X
OE1B
L
L
L
L
L
L
L
H
L
H
L
OE2B
L
L
L
L
L
L
L
H
H
L
L
1B
H
L
H
L
B
(1)
B
(1)
B
(1)
Z
Active
Z
Active
Outputs
2B
H
L
B
(1)
B
(1)
H
L
B
(1)
Z
Z
Active
Active
NOTES:
1. Output level before the indicated steady-state input conditions were
established.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
3
IDT54/74FCT16260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 5.0V ±10%; Military: T
A
= -55°C to +125°C, V
CC
= 5.0V ±10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
OS
V
H
I
CCL
I
CCH
I
CCZ
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current (Input pins)
(5)
Input HIGH Current (I/O pins)
(5)
Input LOW Current (Input pins)
(5)
Input LOW Current (I/O pins)
(5)
High Impedance Output Current
(3-State Output pins)
(5)
Clamp Diode Voltage
Short Circuit Current
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max.
V
IN
= GND or V
CC
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
—
V
CC
= Max.
V
O
= 2.7V
V
O
= 0.5V
V
I
= GND
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
Min.
2
—
—
—
—
—
—
—
—
–80
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
–0.7
–140
100
5
Max.
—
0.8
±1
±1
±1
±1
±1
±1
–1.2
–250
—
500
V
mA
mV
µA
µA
Unit
V
V
µA
5v16-link
OUTPUT DRIVE CHARACTERISTICS
Symbol
I
O
V
OH
Parameter
Output Drive Current
Output HIGH Voltage
Test Conditions
(1)
V
CC
= Max., V
O
= 2.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –3mA
I
OH
= –12mA MIL
I
OH
= –15mA IND
I
OH
= –24mA MIL
I
OH
= –32mA IND
(4)
V
OL
I
OFF
Output LOW Voltage
Input/Output Power Off Leakage
(5)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 0V, V
IN
or V
O
≤
4.5V
I
OL
= 48mA MIL
I
OL
= 64mA IND
—
—
±1
µA
—
0.2
0.55
V
2
3
—
V
Min.
–50
2.5
2.4
Typ.
(2)
—
3.5
3.5
Max.
–180
—
—
Unit
mA
V
V
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ±5µA at T
A
= -55°C.
4
IDT54/74FCT16260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
One Output Port Enabled
LExx = V
CC
One Input Bit Toggling
One Output Bit Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
One Output Port Enabled
LExx = V
CC
One Input Bit Toggling
One Output Bit Toggling
V
CC
= Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
One Output Port Enabled
LExx = V
CC
Twelve Input Bits Toggling
Twelve Output Bits Toggling
Min.
—
V
IN
= V
CC
V
IN
= GND
—
Typ.
(2)
0.5
60
Max.
1.5
100
Unit
mA
µ A/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
0.6
1.5
mA
—
0.9
2.3
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
1.8
3.5
(5)
—
4.8
12.5
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current (I
CCL
,
I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
5
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