Ordering number : ENN6123A
CMOS IC
LC72722, 72722M, 72722PM
Single-Chip RDS
Signal-Processing System LSI
Overview
The LC72722 and LC72722M, LC72722PM are single-
chip system ICs that implement the signal processing
required by the European Broadcasting Union RDS (Radio
Data System) standard and by the US NRSC (National
Radio System Committee) RDBS (Radio Broadcast Data
System) standard. These ICs include band-pass filter,
demodulator, synchronization, and error correction circuits
as well as data buffer RAM on chip and perform effective
error correction using a soft-decision error correction
technique.
Functions
• Band-pass filter: Switched capacitor filter (SCF)
• Demodulator: RDS data clock regeneration and
demodulated data reliability information
• Synchronization: Block synchronization detection (with
variable backward and forward protection conditions)
• Error correction: Soft-decision/hard-decision error
correction
• Buffer RAM: Adequate for 24 blocks of data (about 500
ms) and flag memory
• Data I/O: CCB interface (power on reset)
• Two synchronization detection circuits provide
continuous and stable detection of the synchronization
timing.
• Data can be read out starting with the backward-
protection block data after a synchronization reset.
• Bit slip detection and correction
• Low spurious radiation
• Fully adjustment free
• Operating power-supply voltage: 4.5 to 5.5 V
• Operating temperature: –40 to +85°C
• Package: LC72722 : DIP24S
LC72722M : MFP24S
LC72722PM : MFP24
Package Dimensions
unit: mm
3067A-DIP24S
[LC72722]
21.0
24
13
7.62
6.4
1
0.9
12
• Error correction capability improved by soft-decision
error correction
• The load on the control microprocessor can be reduced
by storing decoded data in the on-chip data buffer RAM.
(0.71)
1.78
0.48
0.95
0.51min
3.3 3.9max
(3.25)
Features
SANYO: DIP24S
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
51202AS (OT)/83199TH (OT) No. 6123-1/15
0.25
LC72722, 72722M, 72722PM
unit: mm
unit: mm
3112A-MFP24S
[LC72722M]
24
13
3045C-MFP24
[LC72722PM]
15.2
24
13
10.5
5.4
7.6
7.9
1.7max
12.5
0.15
0.63
1
12
1
(0.62)
1.27
0.35
12
0.15
0.1 1.5
(2.15)
0.35
1.0
(0.75)
2.35max
Pin Assignment
VREF 1
MPXIN 2
Vdda 3
Vssa 4
FLOUT 5
CIN 6
T1 7
T2 8
T3(RDCL) 9
T4(RDDA) 10
T5(RSFT) 11
XOUT 12
24 SYR
23 CE
22 DI
21 CL
20 DO
LC72722
19 RDS-ID
LC72722M
18 SYNC
LC72722PM
17 T7(CORREC/ARI-ID/TA/BEO)
16 T6(ERROR/57K/TP/BE1)
15 Vssd
14 Vddd
13 XIN
Block Diagram
+5V
Vdda
VREF
FLOUT
Top view
A12363
0.1
SANYO: MFP24S
SANYO: MFP24
CIN
CLOCK
RECOVERY
(1187.5 Hz)
Vddd
+
REFERENCE
VOLTAGE
Vssa
57 kHz
BPF
(SCF)
VREF
ANTIALIASING
FILTER
SMOOTHING
FILTER
–
PLL
(57 kHz)
Vssd
MPXIN
DATA
DECODER
RDS-ID
DO
CL
DI
CE
T1
T2
T3 to T7
CCB
RAM
(24 BLOCK DATA)
ERROR CORRECTION
(SOFT DECISION)
SYNC/EC CONTROLLER
SYNC
SYR
MEMORY CONTROL
TEST
CLK(4.332 MHz)
SYNC
DETECT-1
OSC/DIVIDER
SYNC
DETECT-2
XIN
XOUT
A12364
No. 5602-2/15
0.65
+5V
LC72722, 72722M, 72722PM
Pin Functions
Pin No.
Pin name
Function
I/O
Pin circuit
Vdda
1
VREF
Reference voltage output (Vdda/2)
Output
Vssa
Vdda
2
MPXIN
Baseband (multiplexed) signal input
Input
A12365
Vssa
A12366
5
FLOUT
Subcarrier output (filter output)
Output
–
+
A12367
Vdda
6
CIN
Subcarrier input (comparator input)
Input
Vssa
VREF
3
4
Vdda
Vssa
Analog system power supply (+5 V)
Analog system ground
—
—
—
—
A12368
Vddd
12
XOUT
Crystal oscillator output (4.332/8.664 MHz)
Output
XIN
XOUT
Vssd
A12369
13
XIN
Crystal oscillator input (external reference signal input)
7
T1
Test input (This pin must always be connected to ground.)
Test input (standby control)
0: Normal operation, 1: Standby state (crystal oscillator stopped)
Test I/O (RDS clock output)
Test I/O (RDS data output)
Test I/O (soft-decision control data output)
Test I/O (error status output, regenerated carrier output,
TP output, error block count output)
Input
S
Vssd
A12370
8
9
10
11
16
T2
T3 (RDCL)
T4 (RDDA)
T5 (RSFT)
T6 (ERROR/57K/TP/BE1)
I/O*
Vssd
A12371
17
18
19
Test I/O (Error correction status output, SK detection output,
T7 (CORREC/ARI-ID/TA/BE0) TA output, error block count output)
SYNC
RDS-ID
Block synchronization detection output
RDS detection output
Output
Vssd
A12372
20
21
22
23
24
14
15
DO
CL
DI
CE
SYR
Vddd
Vssd
Data output
Clock input
Data input
Chip enable
Synchronization and RAM address reset (active high)
Digital system power supply (+5 V)
Digital system ground
—
—
Input
Serial data interface (CCB)
S
Vssd
—
—
A12373
Note:
*
Normally function as an output pin. Used as an I/O pin in test mode, which is not available to user applications.
No. 5602-3/15
LC72722, 72722M, 72722PM
Specifications
Absolute Maximum Ratings
at Ta = 25°C, Vssd = Vssa = 0 V
Parameter
Maximum supply voltage
Symbol
V
DD
max
V
IN
1 max
Maximum input voltage
V
IN
2 max
V
IN
3 max
V
O
1 max
Maximum output voltage
V
O
2 max
V
O
3 max
I
O
1 max
Maximum output current
I
O
2 max
I
O
3 max
Allowable power dissipation
Pd max
Conditions
Vddd, Vdda: Vdda
≤
Vddd +0.3 V
CL, DI, CE, SYR, T1, T2, T3, T4, T5, T6, T7, SYNC
XIN
MPXIN, CIN
DO, SYNC, RDS-ID, T3, T4, T5, T6, T7
XOUT
FLOUT
DO, T3, T4, T5, T6, T7
XOUT, FLOUT
SYNC, RDS-ID
LC72722:DIP24S:
Ta
≤
85°C
LC72722M:MFP24S:
LC72722PM:MFP24:
Operating temperature
Storage temperature
Topr
Tstg
Ratings
–0.3 to +7.0
–0.3 to +7.0
–0.3 to Vddd +0.3
–0.3 to Vdda +0.3
–0.3 to +7.0
–0.3 to Vddd +0.3
–0.3 to Vdda +0.3
6.0
3.0
20.0
350
150
175
–40 to +85
–55 to +125
Unit
V
V
V
V
V
V
V
mA
mA
mA
mW
mW
mW
°C
°C
Allowable Operating Ranges
at Ta = –40 to +85°C, Vssd = Vssa = 0 V
Parameter
Symbol
V
DD
1
V
DD
2
V
IH
V
IL
V
O
V
IN
1
Input amplitude
V
IN
2
V
XIN
Guaranteed crystal oscillator frequencies
Crystal oscillator frequency deviation
Data setup time
Data hold time
Clock low-level time
Clock high-level time
CE wait time
CE setup time
CE hold time
CE high-level time
Data latch change time
Xtal
TXtal
t
SU
t
HD
t
CL
t
CH
t
EL
t
ES
t
EH
t
CE
t
LC
t
DC
Data output time
t
DH
DO, CL: Differs depending on the value of the
pull-up resistor used.
DO, CE: Differs depending on the value of the
Conditions
Vddd, Vdda: Vddd = Vdda
Vddd: Serial data hold voltage
CL, DI, CE, SYR, T1, T2
CL, DI, CE, SYR, T1, T2
DO, SYNC, RDS-ID, T3, T4, T5, T6, T7
MPXIN : f = 57 ±2 kHz
MPXIN : 100% modulation composite
XIN
XIN, XOUT : CI
≤
120
Ω
(XS = 0)
XIN, XOUT : CI
≤
70
Ω
(XS = 1)
XIN, XOUT : f
O
= 4.322 MHz, 8.664 MHz
DI, CL
DI, CL
CL
CL
CE, CL
CE, CL
CE, CL
CE
0.75
0.75
0.75
0.75
0.75
0.75
0.75
20
1.15
0.46
0.46
100
400
4.332
8.664
±100
1500
Ratings
min
4.5
2.0
0.7 Vddd
0
6.5
0.3 Vddd
6.5
50
typ
5.0
max
5.5
Unit
V
V
V
V
V
mVrms
mVrms
mVrms
MHz
MHz
ppm
µs
µs
µs
µs
µs
µs
µs
ms
µs
µs
µs
Supply voltage
Input high-level voltage
Input low-level voltage
Output voltage
Electrical Characteristics
at Ta = –40 to +85°C, Vssd = Vssa = 0 V
Parameter
Symbol
Rmpxin
Rcin
Rf
fc
Conditions
MPXIN–Vssa : f = 57 kHz
CIN–Vssa : f = 57 kHz
XIN
FLOUT
56.5
2.5
28
Ratings
min
typ
43
100
1.0
57.0
3.0
31
57.5
3.5
34
max
Unit
kΩ
kΩ
MΩ
kHz
kHz
dB
Input resistance
Internal feedback resistance
Center frequency
–3 dB bandwidth
Gain
BW – 3 dB FLOUT
Gain
MPXIN–FLOOUT : f = 57 kHz
Continued on next page.
No. 5602-4/15
LC72722, 72722M, 72722PM
Continued from preceding page.
Parameter
Symbol
Att1
Stop band attenuation
Att2
Att3
pull-up resistor used.Reference voltage output
Hysteresis
Output low-level voltage
Vref
V
HIS
V
OL
1
V
OL
2
I
IH
1
I
IH
2
I
IL
1
I
IL
2
I
OFF
Idd
Conditions
FLOUT :
∆f
= ±7 kHz
FLOUT : f < 45 kHz, f > 70 kHz
FLOUT : f < 20 kHz
VREF : Vdda = 5 V
CL, DI, CE, SYR, T1, T2
DO, T3, T4, T5, T6, T7 : I = 2 mA
SYNC, RDS-ID : I = 8 mA
CL, DI, CE, SYR, T1, T2 : V
I
= 6.5 V
XIN : V
I
= Vddd
CL, DI, CE, SYR, T1, T2 : V
I
= 0 V
XIN : V
I
= 0 V
DO, SYNC, RDS-ID, T3, T4, T5, T6, T7 :
V
O
= 6.5 V
Vddd + Vdda
9
2.0
2.0
Ratings
min
30
40
50
2.5
0.1 Vddd
0.4
0.4
5.0
11
5.0
11
5.0
typ
max
Unit
dB
dB
dB
V
V
V
V
µA
µA
µA
µA
µA
mA
Input high-level current
Input low-level current
Output off leakage current
Current drain
CCB Output Data Format
• Each block of output data consists of 32 bits (4 bytes), of which 2 bytes are RDS data and 2 bytes are flag data.
• Any number of 32-bit output data blocks can be output consecutively.
• When there is no data that can be read out in the internal memory, the system outputs blocks of all-zero data
consecutively.
• If data readout is interrupted, the next read operation starts with the 32-bit data block whose readout was interrupted.
However, if only the last bit remains to be read, it will not be possible to reread that whole block.
• The check bits (10 bits) are not output.
• The data valid/invalid decision is made by referencing the error information flags (E0 to E2) must not be referred to.
• When the first leading bits are not "1010", the read in data is invalid, and the read operation is cancelled.
CCB address 6C
B B B B A A A A
0 1 2 3 0 1 2 3
0
0
1
1
0
1
1
0
DI
Output data/first bit
DO
1
0 1
Last bit
O
R R A S
D D D D D D
0 W B B B R F F R Y E E E 1 1 1 1 1 1 D D D D D D D D D D
2 1 0 E 1 0 I C 2 1 0 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
D
(8) RDS data
(7) Error information flags
(6) Synchronization established flag
(5) ARI (SK) detection flag
(4) RAM data remaining flag
(3) Consecutive RAM read out possible flag
(2) Offset word information flag
(1) Offset word detection flag
Fixed pattern (1010)
1. Offset word detection flag (1 bit): OWD
OWD
1
0
Offset word detection
Detected
Not detected (protection function operating)
No. 5602-5/15
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