Ordering number : ENN6237
CMOS IC
LC895198
CD-ROM Decoder for 32× ATAPI (IDE) Drives
Overview
The LC895198 is a CD-ROM decoder that supports
ATAPI (IDE) and includes 1 MB of on-chip DRAM.
Functions
•
•
•
•
•
•
CD-ROM ECC function
Sub-code read function
Built-in ATAPI (IDE) I/F (register and other blocks)
CAV audio function
Built-in DVD-ROM I/F (8-bit width)
Built-in 1-Mbit DRAM
• Built-in CAV-AUDIO function
• Built-in intelligent functions (auto buffering, auto
decoding, CD-R support, etc.)
• Built-in subcode P to W buffering function (NO-ECC)
and CD-TEXT support
Package Dimensions
unit: mm
3237-LQFP120
[LC895198]
16.0
14.0
(1.2)
0.4
0.125
Features
• 32× speed supported
16.6MBytes/s (with IORDY)
Operation frequency: 33.8688 MHz
• 32× speed supported
16.6MBytes/s (without IORDY)
Operation frequency: 36 MHz
• CD main channel, C2 flag, and subcode areas in buffer
RAM can be set freely by user
• Built-in batch transfer function (function for sending CD
main channel, C2 flag, subcode, etc., at one time)
• Built-in multi transfer function (function for sending
several blocks at one time)
16.0
14.0
0.4
120
(1.2)
1
0.15
(1.4)
0.1
1.6max
0.5
(0.5)
SANYO: LQFP120
Specifications
Absolute Maximum Ratings
at V
SS
= 0 V
Parameter
Maximum supply voltage
Input/output voltage
Allowable power dissipation
Operating temperature
Storage temperature
Soldering temperature (pin part only)
Input/output power
I
I
, I
O
Symbol
V
DD
max
V
I,
V
O
Pd max
Topr
Tstg
10 s
Per 1 input/output reference cell
Ta = 25°C
Ta = 25°C
Ta
≤
70°C
Conditions
Ratings
–0.3 to +7.0
–0.3 to V
DD
+ 0.3
400
0 to +70
–55 to +125
235
±20
Unit
V
V
mW
°C
°C
°C
mA
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N3099TH (OT) No. 6237-1/10
LC895198
Allowable Operating Ranges
at Ta = 0 to +70°C, V
SS
= 0 V
I
O
cell 5.0 V supply voltage
Parameter
Supply voltage
Input voltage range
Symbol
V
DD
V
IN
Conditions
Ratings
min
4.5
0
typ
5.0
max
5.5
V
DD
Unit
V
V
Internal cell 3.3 V supply voltage
Parameter
Supply voltage
Input voltage range
Symbol
V
DD
V
IN
Conditions
Ratings
min
3.0
0
typ
3.3
max
3.6
V
DD
Unit
V
V
Electrical Characteristics
at Ta = 0 to +70°C, V
SS
= 0 V, V
DD
= 4.5 to 5.5 V
Parameter
Input high-level voltage
Input low-level voltage
Input high-level voltage
Input low-level voltage
Input high-level voltage
Input low-level voltage
Input high-level voltage
Input low-level voltage
Output high-level voltage
Output low-level voltage
Output high-level voltage
Output low-level voltage
Output high-level voltage
Output low-level voltage
Output low-level voltage
Output low-level voltage
Input leak current
Output leak current
Pull-up resistance
Pull-down resistance
The applicable pin sets are as follows.
INPUT
(1)
(2)
(3)
ATPINSEL, CSCTRL, SUA0 to SUA6, BCK, C2PO, LRCK, DSDATA, SBS0, SCOR, WFCK, TEST0 to TEST1, AUDIOCK
ZRESET, ZCS, ZRD, ZWR, CSEL
DA0 to DA2, ZCS1FX, ZCS3FX, ZDIOR, ZDIOW, ZDMACK, ZHRST
Symbol
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OL
V
OL
I
IL
I
OZ
R
UP
R
DN
DRESP, DREQ, HDB0 to HDB7
Conditions
Applicable pins
Ratings
min
2.2
—
2.2
—
2.2
—
2.4
—
V
DD
– 2.1
—
V
DD
– 2.1
—
V
DD
– 2.1
—
—
—
–10
–10
40
40
80
80
typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
max
—
0.8
—
0.8
—
0.8
—
0.8
—
0.4
—
0.4
—
0.4
0.4
0.4
+10
+10
160
160
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
kΩ
kΩ
TTL levels
TTL levels
with pull-up resistor
TTL levels Schmitt
with pull-down resistor
TTL levels
Schmitt
I
OH
= –2 mA
I
OL
= 2 mA
I
OH
= –8 mA
I
OL
= 8 mA
I
OH
= –4 mA
I
OL
= 24 mA
I
OL
= 24 mA
I
OL
= 8 mA
V
I
= V
SS
, V
DD
During high-impedance output
(1)
(9)
DRESP
HDB0 to HDB7
(2), (3), (10)
(9)
(4)
(7), (10)
(8)
(5), (6)
(1), (2), (3), (10)
(5), (7), (8), (10)
(6), (9)
OUTPUT
(4)
(5)
(6)
(7)
(8)
EXCK, DREQ, MCK, MCK3
ZRSTCPU
ZINT, ZINT1, ZSWAIT
DMARQ, HINTRQ
IORDY, ZIOCS16
INOUT
(9)
D0 to D7
(10) DD0 to DD15, ZDASP, ZPDIAG
Note: Pins other than XTAL and XTALCK are not included in DC characteristics.
No. 6237-2/10
LC895198
Recommended Oscillator Circuit Example
LC895198
XTALCK
PN28
R1
XTAL
PN29
R2
C1
C2
A12524
R1 = 1 MΩ
R2 = 15
Ω
C1 = 0
C2 = 47 pF
When the ceramic clock oscillator frequency is 33.8688 MHz:
(The 33.8688 MHz in this recommended example is the third harmonic.)
The exact values of the components are influenced by the printed circuit board used. Consult with the manufacturer of
the oscillator element used to determine these values.
No. 6237-3/10
LC895198
Block Diagram
Data bus[0:7]
*1
EXCK
RAM
Data bus[0:15] Address bus[0:16]
LC895198
Sub-code I/F
10byte FIFO for Sub Q
Address generator
CAV-Audio contorol
CD-DSP
Address generator
*10
DAC
*2
CD-DSP I/F
& SYNC
Detector
De-scramble &
Buffering
Address generator
ECC & EDC
ZRESET
ZRSTCPU
HOST
*3
*4
*5
ZINT0
ZINT1
*6
*7
ZSWAIT
Each Block
XTALCK
XTAL
DVD-ECC
dec
MCK3
MCK
*8
*9
Clock
generator
Each Block
Register
R0-R127
decoder
Reset
Controller
Address generator
Each Block
Bus control
signal
1Mbit
IDE I/F
Based HISIDE
**1
Bus
Arbiter
&
DRAM
controller
Buffer
DRAM
Data output input I/F
Address generator
Micro
controller
Microcontroller
RAM access
Address generator
DVD-ECC I/F
Address generator
A12525
*1
*2
*3
*4
*5
*6
*7
*8
*9
*10
**1
WFCK, SBSO, SCOR
BCK, SDATA, LRCK, C2PO
DD0 to DD15, ZDASP, ZPDIAG
ZCS1FX, ZCS3FX, DA0 to DA2, ZDIOR, ZDIOW, ZDMACK, CSEL
DMARQ, HINTRQ, ZIOCS16, IORDY, ZHRST
ZRD, ZWR, SUA0 to SUA6, ZCS, CSCTRL
D0 to D7
HDB0 to HDB7, DRESP
DREQ
DBCK, DLRCK, DSDATA
HISIDE(WD25C32) is made by WESTERN DIGITAL
No. 6237-4/10
LC895198
Pin Functions
LC895198 Pin Functions 1
(When ATPINSEL (pin 113) is 0)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Pin
V
DD0
DREQ
DRESP
HDB7 (IOP0)
HDB6 (IOP1)
HDB5 (IOP2)
HDB4 (IOP3)
HDB3 (IOP4)
HDB2 (IOP5)
HDB1 (IOP6)
HDB0 (IOP7)
MCK3
V
SS0
V
DD1
V
DD0
DSDATA
DLRCK
DBCK
C2PO
SDATA
BCK
LRCK
EXCK
WFCK
SBSO
SCOR
MCK
XTALCK
XTAL
V
SS0
V
DD1
V
DD0
V
SS0
CSCTRL
ZRD
ZWR
ZCS
SUA0
SUA1
SUA2
SUA3
SUA4
SUA5
SUA6
V
DD1
V
DD0
V
SS0
Type
P
O
I
B
B
B
B
B
B
B
B
O
P
P
P
O
O
O
I
I
I
I
O
I
I
I
O
I
O
P
P
P
P
I
I
I
I
I
I
I
I
I
I
I
P
P
P
3.3 V
5.0 V
Microcontroller register selection signals
Active low/active high selection for the microcontroller CS pin
Microcontroller data read signal input
Microcontroller data write signal input
Register chip select input from the microcontroller
3.3 V
5.0 V
XTALCLK 1/1, 1/2, and stop output
Crystal oscillator circuit input
Crystal oscillator circuit output
Subcode I/O
CD DSP interface
D/A converter output
3.3 V
5.0 V
XTALCLK 1/1, 1/2, and stop output
DVD ECC data I/O
These pins can be switched to function as general-purpose I/O ports by register settings.
5.0 V
DVD ECC data request output
DVD ECC data latch signal input
I
O
INPUT
OUTPUT
B
P
Function
Type
BIDIRECTION
POWER
NC
NOT CONNECT
Continued on next page.
No. 6237-5/10
嵌入式系统
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