Ordering number : ENN7349
CMOS IC
LC75010W
LC75010W Car Audio DSP
Overview
The LC75010W is a car audio DSP IC that integrates the
signal processing required by car audio systems, A/D and
D/A converters, volume control, and other functions on a
single chip. It can implement a car audio system with a
minimal number of external components.
• Supply Voltage and Package Specifications
— DSP core, A/D converter (digital block), D/A
converter (digital block): 3.3 V
— A/D converter (analog block), D/A converter
(analog block), volume control, crystal oscillator:
5V
— Package: 100-pin SQFP (14×14 mm)
Features
• Hardware Functions
— Analog source selector (BTL:1ch, OTL:3 ch)
— 20 bits A/D (2ch)
— 24 bits DSP (core, program memory, data memory)
— SIO (CCB I/F) (CCB is LSB first input.)
— 24 bits D/A (4ch)
— EVR (4ch)
• Software Functions* (See Note.)
— Bass/Mid/Treb
— Bal/Fad
— Fixed equalizer (Front/Rear/separately controlled)
— Loudness control
— Hybrid volume
— Anti-hard clip
— Dedekind (Speaton**)
Note *: Software specifications can be modified in
response to user requests.
• DSP Functions (24 fixed-point DSP)
— Program ROM — 8k words
— Data RAM — 896 words
Package Dimensions
unit: mm
3181C-SQFP100
[LC75010W]
16.0
0.5
14.0
75
76
51
50
100
1
(1.0)
(1.4)
0.5
0.2
26
25
0.145
1.6max
0.1
• CCB is a registered trademark of Sanyo Electric Co., Ltd.
• CCB is Sanyo's original bus format. All bus addresses are managed by Sanyo for this format.
Note
**:
Speaton is a registered trademark of Dedekind R&D. Users who want to develop, manufacture,
or sell electronic equipment that uses Dedekind functions must enter a separate contract with
Dedekind R&D for the use of those functions.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N2103TN (OT) No. 7349-1/12
14.0
SANYO: SQFP100
16.0
LC75010W
Specifications
Absolute Maximum Ratings
at Ta = 25°C, V
SS
= 0 V
Parameter
Supply voltage
(A/D, D/A, volume, etc)
Supply voltage (crystal oscillator)
Symbol
V
DDmax1
V
DDmax2
Pin name
AV
DD1
, AV
DD2
, AV
DD5
, AV
DD6
, AV
DD7
, AV
DD8
, AV
DD9
,
AV
DD10
, AV
DD11
, AV
DD12
XV
DD
DV
DD1
, DV
DD2
, DV
DD3
, DV
DD4
, DV
DD5
, DV
DD6
, AV
DD4
AINRP1, AINRN1, AINLP1, AINLN1, AINRP2,AINLP2,
AINRP3, AINLP3, AINRP4, AINLP4,
VFLI, VFRI, VRLI, VRRI
TEST0, TEST1, TEST2, TEST3, TEST4, TEST5,
TEST6, TEST7, TEST8, TEST9, TEST10,
TEST13, TEST14, PWDB
CL, CE, DI, RSTB, INTB
(Conditions: Audio disabled operating state, Std. Board
installation ; See note)
DO
0
–40
–55
Ratings
min
–0.3
–0.3
–0.3
typ
max
+6.0
+6.0
+4.0
V
DDmax1
+ 0.3
(max +6.0 V)
Unit
V
V
V
Supply voltage
(DSP core block)(I/O I/F, PLL block) V
DDmax3
Maximum input voltage
(A/D, D/A, volume, etc)
Maximum input voltage
(DSP core block)
(I/O I/F block)
V
IN
1
–0.3
V
V
IN
2
V
IN
3
–0.3
–0.3
V
DDmax3
+ 0.3
(max +4.0 V)
V
V
mW
mA
°C
°C
+6.0
830
6.0
85
125
Allowable power dissipation
Maximum output current
Operating temperature
Storage temperature
Pdmax
Io
Topr
Tstg
Note Std. board : 114.3 mm
×
76.2 mm
×
1.5 mm, material ; glass epoxy resin
Allowable Operating Ranges
at Ta = –40 to +85°C, V
SS
D = V
SS
A = 0 V
Parameter
Supply voltage
(analog block)
Supply voltage (crystal oscillator)
Supply voltage
(digital block, PLL)
Symbol
AV
DD5
XV
DD5
DV
DD3.3
V
IHD
V
IHD1
V
ILD
V
ILD1
Full-scale input level
Crystal oscillator frequency
*
Pin name
AV
DD1
, AV
DD2
, AV
DD5
, AV
DD6
, AV
DD7
, AV
DD8
, AV
DD9
,
AV
DD10
, AV
DD11
, AV
DD12
XV
DD
DV
DD1
, DV
DD2
, DV
DD3
, DV
DD4
, DV
DD5
, DV
DD6
, AV
DD4
PWDB, INITB, TEST0, TEST1, TEST2, TEST3, TEST4,
TEST5, TEST6, TEST7, TEST8, TEST9, TEST10,
TEST13, TEST14
CL, CE, DI, RSTB
PWDB, INITB, TEST0, TEST1, TEST2, TEST3, TEST4,
TEST5, TEST6, TEST7, TEST8, TEST9, TEST10,
TEST13, TEST14
CL, CE, DI, RSTB
AINRP1, AINRN1, AINLP1, AINLN1, AINRP2,
AINLP2, AINRP3, AINLP3, AINRP4, AINLP4
X
IN
, X
OUT
16.9344
Ratings
min
+4.75
+4.75
+3.0
0.7
×
DV
DD3.3
0.7
×
AV
DD5
V
SS
V
SS
typ
max
+5.25
+5.25
+3.6
Unit
V
V
V
High-level input voltage
DV
DD3.3
AV
DD5
0.3
×
DV
DD3.3
0.3
×
AV
DD5
0.4
×
AV
DD5
V
V
V
V
Vp-p
MHz
Low-level input voltage
Note*: Consult with the manufacturer of the crystal oscillator element used to verify that the circuit constant values are appropriate for that crystal
oscillator element before using this circuit.
No. N7349-2/12
LC75010W
Electrical Characteristics in the Allowable Operating Ranges
Parameter
Symbol
Pin name
PWDB, RSTB, INTB, CE, CL, DI, TEST0,
TEST1, TEST2, TEST3, TEST4, TEST5, TEST6,
TEST7, TEST8, TEST9, TEST10, TEST13, TEST14
PWDB, RSTB, INTB, CE, CL, DI, TEST0,
TEST1, TEST2, TEST3, TEST4, TEST5, TEST6,
TEST7, TEST8, TEST9, TEST10, TEST13, TEST14
BUSY, DO, TEST11, TEST12 (Microcontroller: 5 V)
High-level output voltage
Low-level output voltage
Analog output level
Reference voltage output
V
OH
V
OL
V
OUT
Vref1
Vref2
Vref3
I
AVDD5
BUSY, DO, TEST11, TEST12 (Microcontroller: 3.3 V)
BUSY, DO, TEST11, TEST12
A
OUT1
, A
OUT2
, A
OUT3
, A
OUT4
Vref1, Vref2, Vref3
(Conditions: Audio disabled operating state, Std. board
installed ; See note)
A
VDD5
= X
VDD5
= 5V, D
VDD3.3
= 3.3 V
(Conditions: Audio disabled operating state, Std. board
installed ; See note)
A
VDD5
= X
VDD5
= 5V, D
VDD3.3
= 3.3 V
(Conditions: Audio disabled operating state, Std. board
installed ; See note)
A
VDD5
= X
VDD5
= 5V, D
VDD3.3
= 3.3 V
(Conditions: Audio disabled operating state, Std. board
installed ; See note)
A
VDD5
= X
VDD5
= 5V, D
VDD3.3
= 3.3 V
2.35
0.6
×
AV
DD5
2.5
2.65
–5
4.5
3.0
5.5
3.6
0.5
Ratings
min
typ
max
5
Unit
High-level input current
I
IH
µA
Low-level input current
I
IL
µA
V
V
V
V
P-P
V
55
72
mA
I
XVDD5
Current drain
I
DVDD3.3
5
7
mA
65
85
mA
Power dissipation
Pd
515
680
mW
Note Std. board : 114.3 mm
×
76.2 mm
×
1.5 mm, material : glass epoxy resin
LC75010W Analog Characteristics
Conditions: Analog system: 5 V, digital system: 3.3 V, fs: 44.1 kHz, signal frequency: 1 kHz, from the analog source selector input to the
volume control circuit output.
Measurement band: 10 Hz to 20 kHz, using the SANYO-specified DSP evaluation board.
Test circuit: LC75010W external circuit structure with the DSP operating in through mode (4-bit shiftup), room temperature
Test equipment: Audio analyzer (Rohde & Schwarz UPD)
Parameter
S/N
Dynamic range
THD+N
Conditions
A-weighted, Input conditions: 2 Vp-p
A-weighted
Input conditions: 1.5 Vp-p. See note.
Ratings
min
85
85
—
typ
90
90
–86
max
—
—
–80
Unit
dB
dB
dB
Note: THD+N shows the optimal characteristics for an input (1.5 Vp-p) that is 3 dB lower than the full-scale input level.
CCB Timing
Parameter
Data setup time
Data hold time
Clock low-level time
Clock high-level time
CE wait time
CE setup time
CE hold time
Data latch change time
Data output time
Symbol
t
SU
t
HD
t
CL
t
CH
t
EL
t
ES
t
EH
t
LC
t
DC
t
DH
DO, CL
DO, CE
DI, CL
DI, CL
CL
CL
CE, CL
CE, CL
CE, CL
Pin name
Ratings
min
0.75
0.75
0.75
0.75
0.75
0.75
0.75
0.75
0.35
typ
max
Unit
µs
µs
µs
µs
µs
µs
µs
µs
µs
No. N7349-3/12
LC75010W
Pin Assignments
Vref1
AVSS12
AVDD12
AINRP1
Ars4
Ars3
AINRN1
AINRP4
AINRP3
AVSS11
AVDD11
AINRP2
AVDD9
AVSS9
Vref3
AINLP2
AVDD10
AVSS10
AINLP3
AINLP4
AINLN1
Als3
82
81
80
79
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
AVSS0
AVSS1
AVDD1
AVDD2
AVSS2
AVSS3
AVB1
DVSS1
DVDD1
TEST0
TEST1
TEST2
TEST3
TEST4
DVSS2
DVDD2
TEST5
TEST6
TEST7
TEST8
TEST9
TEST10
DVB1
DVSS3
DVDD3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Als4
AINLP1
AVSS8
LC75010W
(Top view)
AVDD8
VFLO
VFLI
AOUT1
VFRO
VFRI
AOUT2
AVSS7
AVDD7
Vref2
AVB2
NC
NC
AVSS6
AVDD6
AOUT3
VRLI
VRLO
AOUT4
VRRI
VRRO
AVSS5
AVDD5
XVDD
XVSS
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
TEST12
TEST13
TEST14
DVSS6
AVDD4
VCO
PDO
AVSS4
DVDD4
DVSS4
DVB2
BUSY
PWDB
RSTB
CE
CL
DI
DO
INTB
TEST11
DVSS5
DVDD5
DVDD6
XIN
XOUT
48
49
50
No. N7349-4/12
LC75010W
Pin Functions
Pin No.
97
94
77
80
89
85
92
82
93
81
Pin name
AINRP1
AINRN1
AINLP1
AINLN1
AINRP2
AINLP2
AINRP3
AINLP3
AINRP4
AINLP4
Input/Output (I/O)
I
I
I
I
I
I
I
I
I
I
Analog BTL input (Rch +)
Analog BTL input (Rch -)
Analog BTL input (Lch +)
Analog BTL input (Lch -)
Analog OTL input1 (Rch +)
Analog OTL input1 (Lch +)
Analog OTL input2 (Rch +)
Analog OTL input2 (Lch +)
Analog OTL input3 (Rch +)
Analog OTL input3 (Lch +)
Standby mode (active low)
Setting the PWDB pin to the low level sets the LC75010W to standby mode (also know as "power
down mode").
In standby mode, the DSP system clock and the crystal oscillator are stopped and the whole
LC75010W goes to the stopped state. This pin must be held at the high level during normal
operation.
Reset (active low)
A reset is normally applied at power on, after recovering from a temporary power outage, and after
returning from standby mode ("power down mode").
Interrupt (active low) (Software clip input (0/1))
Provides feedback control to the DSP to prevent clipping when an overflow occurs in the amplifier
output.
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Test pin
Crystal input (384 fs = 16.9344 MHz) (fs = 44.1 kHz)
Crystal output
VCO control
Charge pump output
CCB enable
CCB clock
Data in
Data out
CCB ready monitor
Outputs the state of the DSP CCB receive buffer.
A low-level output from the BUSY pin indicates that the buffer is empty.
A high-level output indicates that command data is present in the receive buffer.
Volume front Lch output
Volume front Lch input
Volume front Rch output
Volume front Rch input
Volume rear Lch output
Volume rear Lch input
Volume rear Rch output
Volume rear Rch input
Function
34
PWDB
I
35
RSTB
I
40
10
11
12
13
14
17
18
19
20
21
22
41
44
45
46
49
50
27
28
36
37
38
39
INTB
TEST0
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
TEST8
TEST9
TEST10
TEST11
TEST12
TEST13
TEST14
XIN
XOUT
VCO
PDO
CE
CL
DI
DO
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
I
O
I
I
I
O
33
BUSY
O
74
73
71
70
58
59
55
56
VFLO
VFLI
VFRO
VFRI
VRLO
VRLI
VRRO
VRRI
O
I
O
I
O
I
O
I
Continued on next page.
No. N7349-5/12
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