Ordering number : EN4988A
CMOS LSI
LC74781, 74781M
On-Screen Display Controller LSI
for VCR Products
Overview
The LC74781 and LC74781M are on-screen display
CMOS LSIs that display characters and patterns on a TV
screen under microprocessor control. The LC74781 and
LC74781M display up to 12 lines of 24 characters, each in
a 12
×
18 dot matrix.
Package Dimensions
unit: mm
3067-DIP24S
[LC74781]
Features
• Display structure: 12 lines
×
24 characters (up to
288 characters)
• Character structure: 12 (horizontal)
×
18 (vertical) dots
• Character sizes: Three size settings each in the vertical
and horizontal directions
• Character set: 128 characters
• Display start position: 64 position settings each in the
vertical and horizontal directions
• Blinking: In individual character units
• Blinking types: Two types with periods of about 0.5 and
1.0 second
• Blanking: Whole font area blanking (12
×
18 dots)
• Background colors: 8 colors (in internal synchronization
mode): 4fSC (NTSC/PAL/PAL-M/
PAL-N)
Background colors: 4 colors (in internal synchronization
mode): 2fSC (NTSC)
Background colors: 1 color (blue) (in internal
synchronization mode): 2fSC
(PAL/PAL-M/PAL-N)
• External control input: 8-bit serial input format
• Built-in sync separator circuit
• Character blanked data output
• Video output: Compound NTSC, PAL, PAL-N and
PAL-M output
SANYO: DIP24S
unit: mm
3045B-MFP24
[LC74781M]
SANYO: MFP24
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
92595HA/63095TH (OT) No. 4988-1/16
LC74781, 74781M
Pin Functions
Pin No.
1
2
3
4
Symbol
V
SS
1
Xtal
IN
Xtal
OUT
CTRL1
Ground
Crystal oscillator connection
Crystal oscillator input switching
Function
Description
Ground connection (digital system ground)
Used to connect the crystal oscillator and capacitor used to generate the internal
synchronization signal, or to input an external clock (2fsc or 4fsc).
Switches between external clock input mode and crystal oscillator mode.
Low = crystal oscillator mode, high = external clock mode
Outputs the blank signal (the OR of the character and border signals). (Outputs a composite
sync signal when MOD0 is high.) Outputs the crystal oscillator clock during reset (when the
RST pin is low), but can be set up to not output this signal by microprocessor command.
Connections for the coil and capacitor that form the oscillator that generates the character
output dot clock.
Outputs the character signal. (Functions as the external synchronization signal discrimination
signal output pin when MOD0 is high, and outputs the state of the judgment as to whether the
external synchronization signal is present or not. Outputs a high level when the synchronization
signal is present.) Outputs the dot clock (LC oscillator) during reset, but can be set up to not
output this signal by microprocessor command.
Serial data input enable input. Serial data input is enabled when low. A pull-up resistor is built in
(hysteresis input).
Serial data input clock input.
A pull-up resistor is built in (hysteresis input).
Serial data input. A pull-up resistor is built in (hysteresis input).
Composite video signal level adjustment power supply pin (analog system power supply).
Composite video signal output
Must be either connected to ground or left open.
Video signal input
Power supply
Sync separator circuit input
Sync separator circuit bias voltage
Composite sync signal output
Vertical synchronization
signal input
NTSC/PAL-M switching input
Composite video signal input
Power supply (+5 V: digital system power supply)
Video signal input for the built-in sync separator circuit (Used for either horizontal
synchronization signal or composite sync signal input when the built-in sync separator circuit is
not used.)
Built-in sync separator circuit bias voltage monitor pin
Built-in sync separator circuit composite sync signal output. (When MOD1 is high, outputs a high
level during internal synchronization and a low level during external synchronization.) (Outputs
the SYN
IN
input signal when the internal sync separator circuit is not used.)
Inputs a vertical synchronization signal created by integrating the SEP
OUT
pin output signal. An
integrator must be attached at the SEP
OUT
pin. This pin must be tied to V
DD
1 if unused.
The setting indicated by this pin takes priority in switching between the NTSC, PAL, PAL-M and
PAL-N formats. A low level selects NTSC after a reset. The microprocessor command NTSC,
PAL, PAL-M, or PAL-N setting is valid. High = PAL-M format.
Controls whether or not the VSYNC signal is input to the SEP
IN
input. Low = VSYNC input,
high = VSYNC not input.
System reset input. A pull-up resistor is built in (hysteresis input).
Power supply (+5 V: digital system power supply)
5
6
7
BLANK
OSC
IN
OSC
OUT
Blanking output
LC oscillator connection
8
CHARA
Character output
9
10
11
12
13
14
15
16
17
18
19
CS
SCLK
SIN
V
DD
2
CV
OUT
NC
CV
IN
V
DD
1
SYN
IN
SEP
C
SEP
OUT
Enable input
Clock input
Data input
Power supply
Video signal output
20
SEP
IN
CTRL2
21
22
23
24
CTRL3
RST
V
DD
1
SEP
IN
input control
Reset input
Power supply (+5 V)
No. 4988-2/16
LC74781, 74781M
Pin Assignment
Specifications
Absolute Maximum Ratings
at Ta = 25°C
Parameter
Maximum supply voltage
Maximum input voltage
Maximum output voltage
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
V
DD
max
V
IN
max
V
OUT
max
Pd max
Topr
Tstg
V
DD
1 and V
DD
2 pins
All pins
BLANK, CHARA and SEP
OUT
pins
Ta = 25°C
Conditions
Ratings
V
SS
– 0.3 to V
SS
+ 7.0
V
SS
– 0.3 to V
DD
+ 0.3
V
SS
– 0.3 to V
DD
+ 0.3
350
–30 to +70
–40 to +125
Unit
V
V
V
mW
°C
°C
Allowable Operating Ranges
at Ta = –30 to +70°C
Parameter
Supply voltage
Symbol
V
DD
1
V
DD
2
V
IH
1
V
IH
2
V
IL
1
V
IL
2
R
PU
V
IN
1
V
IN
2
V
IN
3
F
OSC
1
F
OSC
1
F
OSC
1
F
OSC
1
Oscillator frequency
F
OSC
1
F
OSC
1
F
OSC
1
F
OSC
1
F
OSC
2
V
DD
1 pin
V
DD
2 pin
RST, CS, SIN and SCLK pins
CTRL1, CTRL2, CTRL3 and SEP
IN
pins
RST, CS, SIN and SCLK pins
CTRL1, CTRL2, CTRL3 and SEP
IN
pins
RST, CS, SIN and SCLK pins, applies to pins set
by options.
CV
IN
pin: V
DD
1 = 5 V
SYN
IN
pin: V
DD
1 = 5 V
Xtal
IN
pin (in external clock input mode),
f
in
= 2fsc or 4fsc: V
DD
1 = 5 V
Xtal
IN
and Xtal
OUT
oscillator pins (2fsc: NTSC)
Xtal
IN
and Xtal
OUT
oscillator pins (4fsc: NTSC)
Xtal
IN
and Xtal
OUT
oscillator pins (2fsc: PAL)
Xtal
IN
and Xtal
OUT
oscillator pins (4fsc: PAL)
Xtal
IN
and Xtal
OUT
oscillator pins (2fsc: PAL-M)
Xtal
IN
and Xtal
OUT
oscillator pins (4fsc: PAL-M)
Xtal
IN
and Xtal
OUT
oscillator pins (2fsc: PAL-N)
Xtal
IN
and Xtal
OUT
oscillator pins (4fsc: PAL-N)
OSC
IN
and OSC
OUT
oscillator pins (LC oscillator)
5
0.10
7.159
14.318
8.867
17.734
7.151
14.302
7.164
14.328
10
Conditions
min
4.5
4.5
0.8 V
DD
1
0.7 V
DD
1
V
SS
– 0.3
V
SS
– 0.3
25
50
2.0
2.0
2.5
5.0
typ
5.0
5.0
max
5.5
1.27 V
DD
1
V
DD
1 + 0.3
V
DD
1 + 0.3
0.2 V
DD
1
0.3 V
DD
1
90
Unit
V
V
V
V
V
V
kΩ
Vp-p
Vp-p
Vp-p
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Input high level voltage
Input low level voltage
Pull-up resistance
Composite video input voltage
Input voltage
Note: If the Xtal
IN
pin is used in clock input mode, be sure to prevent input noise from becoming a problem.
No. 4988-3/16
LC74781, 74781M
Electrical Characteristics
at Ta = –30 to +70°C, V
DD
1 = 5 V unless otherwise specified
Parameter
Input off leakage current
Output off leakage current
Output high level voltage
Output low level voltage
Symbol
I
leak
1
I
leak
2
V
OH
1
V
OL
1
I
IH
I
IL
Operating current drain
I
DD
1
I
DD
2
Sync level
V
SN
V
PD
V
CBL
V
CBH
V
RSL
V
RSH
V
BK
0
V
BK
1
V
CHA
CV
IN
pin
CV
OUT
pin
BLANK, CHARA and SEP
OUT
pins: V
DD
1 = 4.5 V,
I
OH
= –1.0 mA
BLANK, CHARA and SEP
OUT
pins: V
DD
1 = 4.5 V,
I
OH
= 1.0 mA
RST, CS, SIN, SCLK, CTRL1, CTRL3 and SEP
IN
pins:
V
IN
= V
DD
1
CTRL1, CTRL2, CTRL3 and OSC
IN
pins: V
IN
= V
SS
1
V
DD
1 pin; all outputs: open, Xtal: 7.159 MHz,
LC: 8 MHz
V
DD
2 pin: V
DD
2 = 5 V
CV
OUT
pin
CV
OUT
pin
CV
OUT
pin
CV
OUT
pin
CV
OUT
pin
CV
OUT
pin
CV
OUT
pin
CV
OUT
pin
CV
OUT
pin
V
DD
1 = 5.0 V,
V
DD
2 = 5.0 V
V
DD
1 = 5.0 V,
V
DD
2 = 5.0 V
V
DD
1 = 5.0 V,
V
DD
2 = 5.0 V
V
DD
1 = 5.0 V,
V
DD
2 = 5.0 V
V
DD
1 = 5.0 V,
V
DD
2 = 5.0 V
V
DD
1 = 5.0 V,
V
DD
2 = 5.0 V
V
DD
1 = 5.0 V,
V
DD
2 = 5.0 V
V
DD
1 = 5.0 V,
V
DD
2 = 5.0 V
V
DD
1 = 5.0 V,
V
DD
2 = 5.0 V
*1
*2
*1
*2
*1
*2
*1
*2
*1
*2
*1
*2
*1
*2
*1
*2
*1
*2
0.70
0.91
1.31
1.53
1.00
1.21
1.63
1.84
1.47
1.68
1.99
2.19
1.42
1.63
1.99
2.19
2.58
2.78
0.82
1.03
1.43
1.65
1.12
1.33
1.75
1.96
1.59
1.80
2.11
2.31
1.54
1.75
2.11
2.31
2.70
2.90
–1
15
20
0.94
1.15
1.55
1.77
1.24
1.45
1.87
2.08
1.71
1.92
2.23
2.43
1.66
1.87
2.23
2.43
2.82
3.02
3.5
1.0
1
Conditions
min
typ
max
1
1
Unit
µA
µA
V
V
µA
µA
mA
mA
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Input current
Pedestal level
Color burst low level
Color burst high level
Background color low level
Background color high level
Border level 0
Border level 1
Character level
Note: 1. When the sync level is 0.8 V.
2. When the sync level is 1.0 V.
Timing Characteristics
at Ta = –30 to +70°C, V
DD
1 = 5 ± 0.5 V
Parameter
Minimum input pulse width
Symbol
t
W (SCLK)
t
W (CS)
t
SU (CS)
t
SU (SIN)
t
h (CS)
t
h (SIN)
t
word
t
wt
SCLK pin
CS pin (the period when CS is high)
CS pin
SIN pin
CS pin
SIN pin
8-bit data write time
RAM data write time
Conditions
min
200
1
200
200
2
200
4.2
1
typ
max
Unit
ns
µs
ns
ns
µs
ns
µs
µs
Data setup time
Data hold time
One word write time
No. 4988-4/16
LC74781, 74781M
Serial Data Input Timing
No. 4988-5/16
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
