RD-19240
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®
14-BIT MONOLITHIC TRACKING
RESOLVER-TO-DIGITAL (R/D) CONVERTER
FEATURES
•
Accuracy to 8 Arc Minutes
•
Internal Synthesized Reference
•
+5 Volt Only Option
•
Programmable:
- Resolution: 10-, 12-, or 14-Bit
- Dual Bandwidth
- Tracking Rate
•
Differential Resolver Input Mode
•
Velocity Output Eliminates
Tachometer
•
Built-In-Test (BIT) Output,
No 180° Hangup with AC Reference
DESCRIPTION
The RD-19240 is a low-cost, versatile, state-of-the-art 14-bit mono-
lithic Resolver-to-Digital (R/D) Converter. This single chip converter
offers programmable features such as resolution, bandwidth, velocity
output scaling, and encoder emulation.
Resolution programming allows selection of 10, 12, or 14 bits, with
accuracies to 8 minutes. This feature combines the high tracking rate
of a 10-bit converter with the precision and low-speed velocity reso-
lution of a 14-bit converter in one package. The parallel digital data
and the internal encoder emulation signals (A QUAD B) have inde-
pendent resolution control. Internal encoder emulation permits inhibit-
ing (freezing) the parallel digital data without interrupting the A and B
outputs.
The internal Synthesized Reference section eliminates errors due to
quadrature voltage. The synthesized reference capability ensures
operation with a phase shift up to 45 degrees. The velocity output
(VEL) from the RD-19240, which can be used to replace a tachome-
ter, is a 4 V signal referenced to ground. The full-scale value of VEL
is set by the user with a single resistor.
The converter provides the option of using a second set of filter com-
ponents which can be used in dual bandwidth or switch-on-the-fly
applications.
The RD-19240 converter is available with operating temperature
ranges of -40° to +85°C or -40° to +125°C.
•
-40° to +125°C Operating
Temperature Option
•
Internal Encoder Emulation with
Independent Resolution Control
•
Programmable for LVDT Input
PRELIMINARY
This Preliminary data sheet provides
detailed functional capabilities for product
currently in prototype production. These
specifications are being provided to allow
for electrical design, layout and operation.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
©
2003 Data Device Corporation
Cbw
Rb
Cbw/10
Rb
Cbw
Cbw/10
Data Device Corporation
www.ddc-web.com
REFERENCE
INPUT
RH
VEL2 VEL1
SHIFT
V
E
L
S
J
1
S
J
2
V
E
L
EXTERNAL COMPONENTS
AND 2ND BANDWIDTH
CAPABILITY SECTION
RL BIT
SIGNAL INPUTS
SYNTHESIZED
REFERENCE
SIN
-S
-
+S
CONTROL
TRANSFORMER
GAIN
DEMODULATOR
+
D1 D0
D1
D0
16 BIT
UP/DOWN
COUNTER
HYSTERESIS
VCO
&
TIMING
-
+
VEL
COS
-C
-
+C
+
2
DATA
LATCH
INTERNAL
ENCODER
EMULATION
ZIP_EN
R
V
-VCO
R CLK
VDDP
PCAP
NCAP
VSSP
-5 V
INVERTER
AGND
VDD
GND
VSS
R SET
POWER SUPPLY
INPUTS/GROUND
INH
BIT 1 - BIT 14
EM
EL
D1 D0
A QUAD B A U/B
CB/ZIP
UP/DN
DIGITAL OUTPUTS
RESOLUTION
CONTROL
ENCODER
EMULATION
RD-19240
Pre 1-1-04/05-0
FIGURE 1. RD-19240 BLOCK DIAGRAM
TABLE 1. RD-19240 SPECIFICATIONS
These specifications apply over the rated power supply, temperature,
and reference frequency ranges; 10% signal amplitude variation & 10% harmonic distortion.
PARAMETER
RESOLUTION
FREQUENCY RANGE
ACCURACY
Repeatability
Differential Linearity
REFERENCE
Type
Voltage: differential
single ended
overload
Frequency
Input Impedance
±Sig/Ref Phase Shift (permissible)
SIGNAL INPUT
Type
Voltage: operating
overload
Input Impedance
DIGITAL INPUT/OUTPUT (NOTE 6)
Logic Type
Inputs
UNIT
Bits
Hz
Min
LSB
LSB
(+ RH, - RL)
Differential
10 max
±5 max
±25 continuous 100 transient
DC, 1k to 10k
10M min || 20 pf
45 max
(+S, -S, SIN, +C, -C, COS)
Resolver, differential, groundbased
2 ±15%
±25 continuous
10M min || 10 pF
TTL/CMOS compatible
Logic 0 = 0.8 V max., Logic 1 = 2.0 V min.
Loading=10 µA max P.U. current source to +5 V || 5 pF max., CMOS transient protected
Logic 0 inhibits; Data stable within 150 ns
Logic 0 enables; Data stable within 150 ns (Logic 0 = Transparent)
Logic 1 = High Impedance, Data High Z within 100 ns (note 7)
Logic 0 enables; Data stable within 150 ns (Logic 0 = Transparent)
Logic 1 = High Impedance, Data High Z within 100 ns (note 7)
Mode
Resolver
“
“
LVDT
“
“
ZIP_EN
CMOS Compatible Inputs
SHIFT
UP/DN
A QUAD B
Outputs
Parallel Data (1-14)
Converter Busy (CB)
Built-in-Test (BIT)
D1
0
0
1
-5 V
0
1
D0
0
1
0
0
-5 V
-5 V
Resolution
10 bits
12 bits
14 bits
8 bits
10 bits
12 bits
VALUE
10, 12, or 14 (note 1)
1k to 10k
8 +1 LSB
±1
±2
Vpp
Vp
V
Hz
Ohm
deg
Vrms
V
Ohm
Inhibit (INH)
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 14 (EL)
Resolution and Mode Control (D1 & D0)
(see notes 1 and 8)
Logic 0 enables ZIP, Logic 1 enables CB
Logic 0 = 1.5 V max., Logic 1 = 3.5 V min., negative voltage = -3.5 V min.
Logic
Logic
Logic
Logic
1 selects VEL1 components, Logic 0 selects VEL2 components
0, Gain of pre-charged components will be 4
1, Gain of pre-charged components will be 1/4
0 enables encoder emulation, falling edge latches encoder resolution
10, 12, or 14 parallel lines; natural binary angle positive logic
0.25 to 0.75 µs positive pulse leading edge initiates counter update
Logic 0 for BIT condition.
±100 LSBs of error with a filter of 500 µs total, Loss-of-Signal (LOS) less than 500 mV, or
Loss-of-Reference (LOR) less than 500 mV.
50 pF+
Logic 0; 1 TTL load, 1.6 mA at 0.4 V max.
Logic 1; 10 TTL loads, -0.4 mA at 2.8 V min
Logic 0; 100 mV max. driving CMOS
Logic 1; +5 V supply minus 100 mV min driving CMOS High Z; 10 uA || 5 pF max.
Drive Capability
Data Device Corporation
www.ddc-web.com
3
RD-19240
Pre 1-1-04/05-0
TABLE 1. RD-19240 SPECIFICATIONS (CONT.)
PARAMETER
DIGITAL INPUT/OUTPUT
(CONT) (NOTE 6)
A, B
Zero Index Pulse (ZIP)
DYNAMIC
CHARACTERISTICS
Resolution
Tracking Rate-min (note 4)
Bandwidth(Closed Loop) Max
Ka (acceleration constant
- see note 2)
A1
A2
A
B
Acceleration (1 LSB lag)
Settling Time(179° step)
UNIT
VALUE
APPLICATIONS
The low cost, small size, high accuracy, and versatile perfor-
mance of the RD-19240 converter make it ideal for use in mod-
ern high performance industrial and automotive control systems.
It is ideal for users who wish to use a resolver input in their
encoder-based system. Typical applications include motor con-
trol, factory automation, hybrid electric vehicles, and steering.
Incremental Encoder Output
With the ZIP_EN pad tied to ground
“Logic 0,” this ZIP output is active
(at maximum bandwidth)
bits
rps
Hz
1/sec
2
1/sec
1/sec
1/sec
1/sec
deg/s
2
msec
10
1152
1200
5.7M
19.5
295k
2400
1200
2M
2
12
288
1200
5.7M
19.5
295k
2400
1200
500k
8
14
72
600
1.4M
4.9
295k
1200
600
30k
20
THEORY OF OPERATION
The RD-19240 converter is a single CMOS custom monolithic
chip. It is implemented using mixed signal CMOS technology
which merges precision analog circuitry with digital logic to form
a complete high-performance tracking resolver-to-digital convert-
er. For user flexibility and convenience, the converter bandwidth,
dynamics, and velocity scaling are externally set with passive
components.
FIGURE 1 is the RD-19240 Functional Block Diagram. The con-
verter operates with ±5 V DC power supplies. Analog signals are
referenced to analog ground, which is at ground potential. The
converter is made up of two main sections; a converter and a dig-
ital interface. The converter front-end consists of sine and cosine
differential input amplifiers. These inputs are protected to ±25 V
with 2 kΩ resistors and diode clamps to the ±5 V DC supplies.
These amplifiers feed the high accuracy Control Transformer
(CT). Its other input is the 14-bit digital angle
φ.
Its output is an
analog error angle, or difference angle, between the two inputs.
The CT performs the ratiometric trigonometric computation of
SINθCOSφ - COSθSINφ = SIN(θ-φ) using amplifiers, switches,
logic and capacitors in precision ratios.
Note: The error output of the CT is normally sinusoidal, but
in LVDT mode, it is triangular (linear) and can be used
to convert any linear transducer output.
The converter accuracy is limited by the precision of the com-
puting elements in the CT. For enhanced accuracy, the CT in
these converters uses capacitors in precision ratios, instead of
the more conventional precision resistor ratios. Capacitors used
as computing elements with op-amps need to be sampled to
eliminate voltage drifting. Therefore, the circuits are sampled at a
high rate (70 kHz) to eliminate this drifting and at the same time
to cancel out the op-amp offsets.
The error processing is performed using the industry standard
technique for type II tracking R/D converters. The DC error is
integrated yielding a velocity voltage which in turn drives a volt-
age-controlled oscillator (VCO). This VCO is an incremental inte-
grator (constant voltage input to position rate output) which,
together with the velocity integrator, forms a type II servo feed-
back loop. A lead in the frequency response is introduced to sta-
bilize the loop, and a lag at higher frequency is introduced to
RD-19240
Pre 1-1-04/05-0
VELOCITY
CHARACTERISTICS
Positive for increasing angle
Polarity
V
±4 (at nominal ps)
Voltage Range(Full Scale)
%
10 typ.
20 max.
Scale Factor Error
PPM/C 100 typ.
Scale Factor TC
%
0.75 typ. 1.3 max.
Reversal Error
%
0.5 typ
Linearity
mV 5 typ.
10 max.
Zero Offset
µV/C 15 typ.
Zero Offset TC
kΩ
8 min.
Load
Noise
Vp/V 1 typ.
POWER SUPPLIES
Nominal Voltage
Voltage Range
Max Volt. w/o Damage
Current
TEMPERATURE RANGE
Operating (case)
-AXX
-2XX
Storage
MOISTURE SENSITIVITY
LEVEL (STANDARD PORT)
(notes 6, 7 and 9)
+5
-5
±5
±5
+7
-7
14 typ, 22 max (each)
V
%
V
mA
°C
°C
°C
-40 to +125
-40 to +85
-65 to +150
Level 2 tested in accordance with
JDEC spec J-STD-020
PHYSICAL
CHARACTERISTICS
Size
FS Package
in(mm) 0.39 x 0.39 (10.0 x 10.0)
52-pin MQFP
LS Package
64-pad plastic LPCC in(mm) 0.35 x 0.35 (9.0 x 9.0)
TABLE 1 notes:
1. Unused data bits are set to logic “0”.
2. For Ka definition, see the RDC-19220/RD-19230 Series Converters Applications
Manual (MN-19220XX-001) acceleration lag section.
3. If the frequency is between 47Hz and 1kHz, then there may be 1 LSB of jitter at
quadrant boundaries.
4. See text, General Setup Considerations.
5. When using internally generated -5V the internal -5V charge pump when mea-
sured at the converter pad, may be as low as -20% (or -4V).
6. Any unused input pads may be left floating. All TTL and CMOS input pads are
internally pulled up to +5 volts.
7. High Z refers to parallel data only.
8. In LVDT mode, bit 12 is LSB for 10-bit mode resolution.
9. +5V supply is connected to pin 33 and the underside pad of the LPCC package.
See Mechanical drawing and pin-out table.
Data Device Corporation
www.ddc-web.com
4
reduce the gain and ripple at the carrier frequency and above.
The settings of the various error processor gains and break fre-
quencies are done with external resistors and capacitors so that
the converter loop dynamics can be easily controlled by the user.
GENERAL SETUP CONDITIONS
DDC has external component selection software that considers all
the criteria below and, in a simple fashion, asks the key parame-
ters (carrier frequency, resolution, bandwidth, and tracking rate) to
derive the external component values. For detailed setup informa-
tion refer to the RD/RDC Series Converters Applications Manual
(document #MN-19220XX-001) available at www.ddc-web.com.
The following recommendations should be considered when
installing the RD-19240 Resolver-to-Digital (R/D) converter:
1) When setting the bandwidth (BW) and Tracking Rate (TR)
(selecting five external components), the system require-
ments need to be considered. For the greatest noise immuni-
ty, select the minimum BW and TR the system will allow.
2) Power supplies are ±5 V DC. For lowest noise performance it
is recommended that a 0.1µF or larger cap be connected from
each supply to ground near the converter package. When
using a +5 V and -5 V supply to power the converter, pads 22,
23, 25, and 26 must be no connection.
3) This converter has two internal ground planes, which reduce
noise to the analog input due to digital ground currents. The
resolver inputs and velocity output are referenced to AGND.
The digital outputs and inputs are referenced to GND. The
AGND and GND pads must be tied together as close to the
converter package as possible. Not shorting these pads
together as close to the converter package as possible will
cause unstable converter results.
4) The BIT output, which is active low, is activated by an error of
approximately 100 LSBs. During normal operation, for step
inputs or on power up, a large error can exist.
VELOCITY
OUT
VCO
A
2
S
DIGITAL
POSITION
OUT (φ)
TRANSFER FUNCTION AND BODE PLOT
The dynamic performance of the converter can be determined
from its Transfer Function Block Diagrams and its Bode Plots
(open and closed loop). These are shown in FIGURES 2, 3, and 4.
The open loop transfer function is as follows:
Open Loop Transfer Function =
(
S + 1
)
B
S
S
(
10B + 1
)
A
2
2
where:
A is the gain coefficient
A
2
= A
1
A
2
B is the frequency of lead compensation
The components of gain coefficient are error gradient, integrator
gain, and VCO gain. These can be broken down as follows:
- Error Gradient = 0.011 volts per LSB (CT+Error
Amp+Demod with 2 Vrms input)
- Integrator gain =
- VCO Gain =
C
S
F
S
1.1C
BW
volts per second per volt
1
LSBs per second per volt
1.25 R
v
C
vco
C
s
= 10 pF
F
s
= 70 kHz when Rs = 30 kΩ
F
s
= 100 kHz when Rs = 20 kΩ
F
s
= 125 kHz when Rs = 15 kΩ
C
vco
= 50 pF
where:
ERROR PROCESSOR
RESOLVER
INPUT
(θ)
+
-
CT
e
A1 S + 1
B
S
S +1
10B
R
V
, R
B
, and C
BW
are selected by the user to set velocity scaling
and bandwidth.
H=1
FIGURE 3. TRANSFER FUNCTION BLOCK DIAGRAM #2
-1
RB C
BW
VEL
C
BW
/10
RS
-VSUM
VEL
-VCO
50 pf
C
VCO
CT
RESOLVER
INPUT
(θ)
+
GAIN
DEMOD
1
C
S
F
S
11 mV/LSB
±1.25 V
THRESHOLD
R
V
GAIN = 4
2A
OPEN LOOP
B
A
-6
db
2d
b/o
(CRITICALLY DAMPED)
(B = A/2)
16 BIT
UP/DOWN
COUNTER
ct
ω
(rad/sec)
10B
/oc
t
R1
VCO
GAIN = 0.4
-
f
BW
= BW (Hz) =
H=1
DIGITAL
OUTPUT
(φ)
2A
π
CLOSED LOOP
2A
2 2A
ω
(rad/sec)
FIGURE 2. TRANSFER FUNCTION BLOCK DIAGRAM #1
Data Device Corporation
www.ddc-web.com
5
FIGURE 4. BODE PLOTS
RD-19240
Pre 1-1-04/05-0
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