F
eatures
•
Integer Unit Based on SPARC V7 High-performance RISC Architecture
•
Optimized Integrated 32/64-bit Floating-point Unit
•
On-chip Peripherals
– EDAC and Parity Generator and Checker
– Memory Interface
Chip Select Generator
Waitstate Generation
Memory Protection
– DMA Arbiter
– Timers
General Purpose Timer (GPT)
Real-time Clock Timer (RTCT)
Watchdog Timer (WDT)
– Interrupt Controller with 5 External Inputs
– General Purpose Interface (GPI)
– Dual UART
Speed Optimized Code RAM Interface
8- or 40-bit boot-PROM (Flash) Interface
IEEE 1149.1 Test Access Port (TAP) for Debugging and Test Purposes
Fully Static Design
Performance: 20 MIPs/5 MFlops (Double Precision) at SYSCLK = 25 MHz
Core Consumption: 1.0W Typ. at 20 MIPs/0.7W typ. at 10 MIPs
Operating Range: 4.5V to 5.5V
(1)
-55°C to +125°C
Tested up to Total Dose of 300 KRADs (Si) according to MIL STD 883 Method 1019
SEU Event Rate Better than 3 E-8 Error/Component/Day (Worst Case)
No Single Event Latch-up below an LET Threshold of 80 MeV/mg/cm
2
Quality Grades: ESCC with 9512/003 and QML-Q or V with 5962-00540
Package: 256 MQFPF; Bare Die
1. For 3.3V capability see the TSC695FL datasheet on the Atmel site.
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Rad-Hard 32-bit
SPARC
Embedded
Processor
TSC695F
Note:
Description
The TSC695F (ERC32 Single-Chip) is a highly integrated, high-performance 32-bit
RISC embedded processor implementing the SPARC architecture V7 specification. It
has been developed with the support of the ESA (European Space Agency), and
offers a full development environment for embedded space applications.
The processor is manufactured using the Atmel 0.5 µm radiation tolerant (≥ 300
KRADs (Si)) CMOS enhanced process (RTP). It has been specially designed for
space, as it has on-chip concurrent transient and permanent error detection.
The TSC695F includes an on-chip Integer Unit (IU), a Floating Point Unit (FPU), a
Memory Controller and a DMA arbiter. For real-time applications, the TSC695F offers
a high security watchdog, two timers, an interrupt controller, parallel and serial inter-
faces. Fault tolerance is supported using parity on internal/external buses and an
EDAC on the external data bus. The design is highly testable with the support of an
On-Chip Debugger (OCD), and a boundary scan through JTAG interface.
Rev. 4118J–AERO–08/04
Block Diagram
Figure 1.
TSC695F Block Diagram
TAP
32-bit
Integer
Unit
DMA
Arbiter
Access
Controller
Wait State
Controller
Address
Interface
EDAC
General Purpose
Interface
UART B
UART A
Interrupt
Controller
Parity
Gen./Check.
DMA Ctrl
Clock
&
Parity
Reset
Gen./Chk.
Managt
32/64-bit
Floating-Point
Unit
Parity
Gen./Chk.
Mem Ctrl
Ready/Busy
Add.+Size+ASI
Error
Managt
General Purpose
Timer
Real Time Clock
Timer
Watch
Dog
Data+Check bits
Parities
GPI bits
RxD, TxD
Interrupts
Pin Descriptions
Table 1.
Pin Descriptions
Signal
RA[31:0]
RAPAR
RASI[3:0]
RSIZE[1:0]
RASPAR
CPAR
D[31:0]
CB[6:0]
DPAR
RLDSTO
ALE
DXFER
LOCK
RD
WE
WRT
MHOLD
MDS
MEXC
PROM8
BA[1:0]
ROMCS
ROMWRT
MEMCS[9:0]
MEMWR
Type
I/O,
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
O
O
I
O
O
For pin assignment, refer to package section.
Active
Description
32-bit registered address bus
Output buffer: 400 pF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHOLD+FHOLD
+BHOLD+FCCV
-
-
-
-
-
-
Output buffer: 400 pF
Output buffer: 400 pF
High
Registered address bus parity
4-bit registered address space identifier
2-bit registered bus transaction size
High
High
Registered ASI and SIZE parity
Control bus parity
32-bit data bus
7-bit check-bit bus
High
High
Low
High
High
High
Low
High
Low
Low
Low
Low
Low
Low
Low
Low
Data bus parity
Registered atomic load-store
Address latch enable
Data transfer
Bus lock
Read access
Write enable
Advanced write
Memory bus hold
Memory data strobe
Memory exception
Select 8-bit wide PROM
Latched address used for 8-bit wide boot PROM
PROM chip select
ROM write enable
Memory chip select
Memory write strobe
2
TSC695F
4118J–AERO–08/04
TSC695F
Table 1.
Pin Descriptions (Continued)
Signal
OE
BUFFEN
DDIR
DDIR
IOSEL[3:0]
IOWR
EXMCS
BUSRDY
BUSERR
DMAREQ
DMAGNT
DMAAS
DRDY
IUERR
CPUHALT
SYSERR
SYSHALT
SYSAV
NOPAR
INULL
INST
FLUSH
DIA
RTC
RxA/RxB
TxA/TxB
GPI[7:0]
GPIINT
EXTINT[4:0]
EXTINTACK
IWDE
EWDINT
WDCLK
CLK2
SYSCLK
RESET
SYSRESET
TMODE[1:0]
DEBUG
TCK
TRST
TMS
TDI
TDO
VCCI/VSSI
VCCO/VSSO
Type
O
O
O
O
O
O
O
I
I
I
O
I
O
O
O
O
I
O
I
O
O
O
O
O
I
O
I/O
O
I
O
I
I
I
I
O
O
I
I
I
I
I
I
I
O
Low
High
Low
Low
High
High
High
High
Active
Low
Low
High
Low
Low
Low
Low
Low
Low
Low
Low
High
Low
Low
Low
Low
Low
High
Low
High
High
High
High
High
Description
Memory output enable
Data buffer enable
Data buffer direction
Data buffer direction
I/O chip select
I/O and exchange memory write strobe
Exchange memory chip select
Bus ready
Bus error
DMA request
DMA grant
DMA address strobe
Data ready during DMA access
IU error
Processor (IU & FPU) halt and freeze
System error
System halt
System availability
No parity
Integer unit nullify cycle
Instruction fetch
FPU instruction flush
Delay instruction annulled
Real Time Clock Counter output
Receive data UART ’A’ and ’B’
Transmit data UART ’A’ and ’B’
GPI input/output
GPI interrupt
External interrupt
External interrupt acknowledge
Internal watch dog enable
External watch dog input interrupt
Watch dog clock
Double frequency clock
System clock
Output reset
System input reset
Factory test mode
Software debug mode
Test (JTAG) clock
Test (JTAG) reset
Test (JTAG) mode select
Test (JTAG) data input
Test (JTAG) data output
Main internal power
Output driver power
Output buffer: 400 pF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Used to check the execute
stage of IU
instruction pipeline
-
Input trigger
-
Input trigger
-
Input trigger
-
-
Input trigger
-
-
-
-
Input trigger
Functional mode=00
-
-
pull-up
≈
37 kΩ
pull-up
≈
37 kΩ
pull-up
≈
37 kΩ
-
-
-
Note:
If not specified, the output buffer type is 150 pF, the input buffer type is TTL.
3
4118J–AERO–08/04
System Architecture
The TSC695F is to be used as an embedded processor requiring only memory and
application specific peripherals to be added to form a complete on-board computer. All
other system support functions are provided by the core.
Figure 2.
System Architecture Based on TSC695F
DMA Unit
Ax[31:0]
Xtd PROM
Xchg Mem
Boot PROM
Master
Local
Memory
Glue
Logic
Xtd RAM
I/O 0
to
I/O 3
DPAR
DMAGNT
DMAREQ
DMAAS
Xtd I/O
(BUFFEN, DDIR)
Xtd general
MEMCtrl
FPU
Memory
Interface
RA[31:0]
CB[6:0]
(ROMCS, EXMCS, IOSEL[3:0], MEMWR, IOWR, OE, BUSRDY,...)
RAMCtrl
(MEMCS[9:0], MEMWR, OE)
SYSCLK
ALE
RAM
Memory
DMA
A[31:0]
IU
DMA
D[31:0]
(0 WS)
Peripherals
User
Application
TSC695F
4
TSC695F
4118J–AERO–08/04
TSC695F
P
roduct
D
escription
Integer Unit
The Integer Unit (IU) is designed for highly dependable space and military applications,
and includes support for error detection. The RISC architecture makes the creation of a
processor that can execute instructions at a rate approaching one instruction per pro-
cessor clock possible.
To achieve that rate of execution, the IU employs a four-stage instruction pipeline that
permits parallel execution of multiple instructions.
•
•
Fetch - The processor outputs the instruction address to fetch the instruction.
Decode - The instruction is placed in the instruction register and is decoded. The
processor reads the operands from the register file and computes the next
instruction address.
Execute - The processor executes the instruction and saves the results in temporary
registers. Pending traps are prioritized and internal traps are taken during this stage.
Write - If no trap is taken, the processor writes the result to the destination register.
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•
All four stages operate in parallel, working on up to four different instructions at a time. A
basic ‘single-cycle’ instruction enters the pipeline and completes infour cycles.
By the time it reaches the write stage, three more instructions have entered and are
moving through the pipeline behind it. So, after the first four cycles, a single-cycle
instruction exits the pipeline and a single-cycle instruction enters the pipeline on every
cycle. Of course, a ’single-cycle’ instruction actually takes four cycles to complete, but
they are called single cycle because with this type of instruction the processor can com-
plete one instruction per cycle after the initial four-cycle delay.
Floating-point Unit
The FLoating Point Unit (FPU) is designed to provide execution of single and double-
precision floating-point instructions concurrently with execution of integer instructions by
the IU. The FPU is compliant to the ANSI/IEEE-754 (1985) floating-point standard.
The FPU is designed for highly dependable space and military applications, and
includes support for concurrent error detection and testability.
The FPU uses a four stage instruction pipeline consisting of fetch, decode, execute and
write stages (F, D, E and W). The fetch unit captures instructions and their addresses
from the data and address buses. The decode unit contains logic to decode the floating-
point instruction opcodes. The execution unit handles all instruction execution. The exe-
cution unit includes a floating-point queue (FP queue), which contains stored floating-
point operate (FPop) instructions under execution and their addresses. The execution
unit controls the load unit, the store unit, and the datapath unit. The FPU depends upon
the IU to access all addresses and control signals for memory access. Floating-point
loads and stores are executed in conjunction with the IU, which provides addresses and
control signals while the FPU supplies or stores the data. Instruction fetch for integer
and floating-point instructions is provided by the IU.
The FPU provides three types of registers: f registers, FSR, and the FP queue. The FSR
is a 32-bit status and control register. It keeps track of rounding modes, floating-point
trap types, queue status, condition codes, and various IEEE exception information. The
floating-point queue contains the floating-point instruction currently under execution,
along with its corresponding address.
5
4118J–AERO–08/04
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