Intel
®
7 Series / C216 Chipset
Family Platform Controller Hub
(PCH)
Datasheet
June 2012
Order Number: 326776-003
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I
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel.
Implementations of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
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Copyright © 2012, Intel Corporation
2
Datasheet
Contents
1
Introduction
............................................................................................................ 43
1.1
About This Manual ............................................................................................. 43
1.2
Overview ......................................................................................................... 46
1.2.1 Capability Overview ................................................................................ 47
1.3
Intel
®
7 Series / C216 Chipset Family SKU Definition ............................................. 54
Signal Description
................................................................................................... 57
2.1
Direct Media Interface (DMI) to Host Controller ..................................................... 59
2.2
PCI Express* .................................................................................................... 59
2.3
PCI Interface .................................................................................................... 60
2.4
Serial ATA Interface........................................................................................... 63
2.5
LPC Interface.................................................................................................... 66
2.6
Interrupt Interface ............................................................................................ 66
2.7
USB Interface ................................................................................................... 67
2.8
Power Management Interface.............................................................................. 69
2.9
Processor Interface............................................................................................ 73
2.10 SMBus Interface................................................................................................ 73
2.11 System Management Interface............................................................................ 74
2.12 Real Time Clock Interface ................................................................................... 74
2.13 Miscellaneous Signals ........................................................................................ 75
2.14 Intel
®
High Definition Audio Link ......................................................................... 76
2.15 Controller Link .................................................................................................. 77
2.16 Serial Peripheral Interface (SPI) .......................................................................... 77
2.17 Thermal Signals ................................................................................................ 78
2.18 Testability Signals ............................................................................................. 78
2.19 Clock Signals .................................................................................................... 79
2.20 LVDS Signals .................................................................................................... 81
2.21 Analog Display /VGA DAC Signals ........................................................................ 82
2.22 Intel
®
Flexible Display Interface (Intel
®
FDI) ........................................................ 82
2.23 Digital Display Signals........................................................................................ 83
2.24 General Purpose I/O Signals ............................................................................... 85
2.25 Manageability Signals ........................................................................................ 90
2.26 Power and Ground Signals .................................................................................. 90
2.27 Pin Straps ........................................................................................................ 93
2.28 External RTC Circuitry ........................................................................................ 97
PCH Pin States.........................................................................................................
99
3.1
Integrated Pull-Ups and Pull-Downs ..................................................................... 99
3.2
Output and I/O Signals Planes and States........................................................... 101
3.3
Power Planes for Input Signals .......................................................................... 113
PCH and System Clocks
......................................................................................... 119
4.1
Platform Clocking Requirements ........................................................................ 119
4.2
Functional Blocks ............................................................................................ 122
4.3
Clock Configuration Access Overview ................................................................. 123
4.4
Straps Related to Clock Configuration ................................................................ 123
Functional Description
........................................................................................... 125
5.1
PCI-to-PCI Bridge (D30:F0) .............................................................................. 125
5.1.1 PCI Bus Interface ................................................................................. 125
5.1.2 PCI Bridge As an Initiator ...................................................................... 126
5.1.2.1 Memory Reads and Writes........................................................ 126
5.1.2.2 I/O Reads and Writes .............................................................. 126
5.1.2.3 Configuration Reads and Writes ................................................ 126
5.1.2.4 Locked Cycles ........................................................................ 126
5.1.2.5 Target / Master Aborts............................................................. 126
5.1.2.6 Secondary Master Latency Timer............................................... 126
5.1.2.7 Dual Address Cycle (DAC) ........................................................ 127
5.1.2.8 Memory and I/O Decode to PCI................................................. 127
5.1.3 Parity Error Detection and Generation ..................................................... 127
5.1.4 PCIRST# ............................................................................................. 128
5.1.5 Peer Cycles ......................................................................................... 128
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Datasheet
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5.2
5.3
5.4
5.5
5.6
5.7
5.1.6 PCI-to-PCI Bridge Model ........................................................................ 128
5.1.7 IDSEL to Device Number Mapping ........................................................... 129
5.1.8 Standard PCI Bus Configuration Mechanism.............................................. 129
5.1.9 PCI Legacy Mode .................................................................................. 129
PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) ..................................... 129
5.2.1 Interrupt Generation ............................................................................. 130
5.2.2 Power Management............................................................................... 130
5.2.2.1 S3/S4/S5 Support ................................................................... 130
5.2.2.2 Resuming from Suspended State ............................................... 131
5.2.2.3 Device Initiated PM_PME Message ............................................. 131
5.2.2.4 SMI/SCI Generation................................................................. 131
5.2.3 SERR# Generation ................................................................................ 132
5.2.4 Hot-Plug .............................................................................................. 132
5.2.4.1 Presence Detection .................................................................. 132
5.2.4.2 Message Generation ................................................................ 132
5.2.4.3 Attention Button Detection ....................................................... 133
5.2.4.4 SMI/SCI Generation................................................................. 133
Gigabit Ethernet Controller (B0:D25:F0) ............................................................. 134
5.3.1 GbE PCI Express* Bus Interface.............................................................. 135
5.3.1.1 Transaction Layer.................................................................... 135
5.3.1.2 Data Alignment ....................................................................... 135
5.3.1.3 Configuration Request Retry Status ........................................... 136
5.3.2 Error Events and Error Reporting ............................................................ 136
5.3.2.1 Data Parity Error ..................................................................... 136
5.3.2.2 Completion with Unsuccessful Completion Status ......................... 136
5.3.3 Ethernet Interface ................................................................................ 136
5.3.3.1 82579 LAN PHY Interface ......................................................... 136
5.3.4 PCI Power Management ......................................................................... 137
5.3.4.1 Wake Up ................................................................................ 137
5.3.5 Configurable LEDs................................................................................. 139
5.3.6 Function Level Reset Support (FLR) ......................................................... 140
5.3.6.1 FLR Steps............................................................................... 140
LPC Bridge (with System and Management Functions) (D31:F0)............................. 140
5.4.1 LPC Interface ....................................................................................... 140
5.4.1.1 LPC Cycle Types ...................................................................... 141
5.4.1.2 Start Field Definition ................................................................ 142
5.4.1.3 Cycle Type / Direction (CYCTYPE + DIR)..................................... 142
5.4.1.4 Size....................................................................................... 142
5.4.1.5 SYNC..................................................................................... 143
5.4.1.6 SYNC Time-Out ....................................................................... 143
5.4.1.7 SYNC Error Indication .............................................................. 143
5.4.1.8 LFRAME# Usage...................................................................... 143
5.4.1.9 I/O Cycles .............................................................................. 144
5.4.1.10 Bus Master Cycles ................................................................... 144
5.4.1.11 LPC Power Management ........................................................... 144
5.4.1.12 Configuration and PCH Implications ........................................... 144
DMA Operation (D31:F0) .................................................................................. 145
5.5.1 Channel Priority.................................................................................... 145
5.5.1.1 Fixed Priority .......................................................................... 145
5.5.1.2 Rotating Priority ...................................................................... 146
5.5.2 Address Compatibility Mode ................................................................... 146
5.5.3 Summary of DMA Transfer Sizes ............................................................. 146
5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words 146
5.5.4 Autoinitialize ........................................................................................ 147
5.5.5 Software Commands ............................................................................. 147
LPC DMA ........................................................................................................ 147
5.6.1 Asserting DMA Requests ........................................................................ 147
5.6.2 Abandoning DMA Requests..................................................................... 148
5.6.3 General Flow of DMA Transfers ............................................................... 149
5.6.4 Terminal Count..................................................................................... 149
5.6.5 Verify Mode ......................................................................................... 149
5.6.6 DMA Request Deassertion ...................................................................... 149
5.6.7 SYNC Field / LDRQ# Rules ..................................................................... 150
8254 Timers (D31:F0) ...................................................................................... 151
5.7.1 Timer Programming .............................................................................. 151
5.7.2 Reading from the Interval Timer ............................................................. 152
5.7.2.1 Simple Read ........................................................................... 152
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Datasheet
5.8
5.9
5.10
5.11
5.12
5.13
5.7.2.2 Counter Latch Command.......................................................... 153
5.7.2.3 Read Back Command .............................................................. 153
8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 154
5.8.1 Interrupt Handling................................................................................ 155
5.8.1.1 Generating Interrupts.............................................................. 155
5.8.1.2 Acknowledging Interrupts ........................................................ 155
5.8.1.3 Hardware/Software Interrupt Sequence ..................................... 156
5.8.2 Initialization Command Words (ICWx) ..................................................... 156
5.8.2.1 ICW1 .................................................................................... 156
5.8.2.2 ICW2 .................................................................................... 157
5.8.2.3 ICW3 .................................................................................... 157
5.8.2.4 ICW4 .................................................................................... 157
5.8.3 Operation Command Words (OCW) ......................................................... 157
5.8.4 Modes of Operation .............................................................................. 157
5.8.4.1 Fully Nested Mode................................................................... 157
5.8.4.2 Special Fully-Nested Mode........................................................ 158
5.8.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 158
5.8.4.4 Specific Rotation Mode (Specific Priority).................................... 158
5.8.4.5 Poll Mode............................................................................... 158
5.8.4.6 Edge and Level Triggered Mode ................................................ 159
5.8.4.7 End of Interrupt (EOI) Operations ............................................. 159
5.8.4.8 Normal End of Interrupt........................................................... 159
5.8.4.9 Automatic End of Interrupt Mode .............................................. 159
5.8.5 Masking Interrupts ............................................................................... 159
5.8.5.1 Masking on an Individual Interrupt Request................................ 159
5.8.5.2 Special Mask Mode.................................................................. 160
5.8.6 Steering PCI Interrupts ......................................................................... 160
Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 160
5.9.1 Interrupt Handling................................................................................ 160
5.9.2 Interrupt Mapping ................................................................................ 161
5.9.3 PCI/PCI Express* Message-Based Interrupts ............................................ 162
5.9.4 IOxAPIC Address Remapping ................................................................. 162
5.9.5 External Interrupt Controller Support ...................................................... 162
Serial Interrupt (D31:F0) ................................................................................. 162
5.10.1 Start Frame......................................................................................... 163
5.10.2 Data Frames........................................................................................ 163
5.10.3 Stop Frame ......................................................................................... 163
5.10.4 Specific Interrupts Not Supported Using SERIRQ ...................................... 164
5.10.5 Data Frame Format .............................................................................. 164
Real Time Clock (D31:F0)................................................................................. 165
5.11.1 Update Cycles...................................................................................... 165
5.11.2 Interrupts ........................................................................................... 166
5.11.3 Lockable RAM Ranges ........................................................................... 166
5.11.4 Century Rollover .................................................................................. 166
5.11.5 Clearing Battery-Backed RTC RAM .......................................................... 166
Processor Interface (D31:F0) ............................................................................ 168
5.12.1 Processor Interface Signals and VLW Messages ........................................ 168
5.12.1.1 INIT (Initialization) ................................................................. 168
5.12.1.2 FERR# (Numeric Coprocessor Error) .......................................... 169
5.12.1.3 NMI (Non-Maskable Interrupt) .................................................. 169
5.12.1.4 Processor Power Good (PROCPWRGD) ....................................... 169
5.12.2 Dual-Processor Issues........................................................................... 169
5.12.2.1 Usage Differences ................................................................... 169
5.12.3 Virtual Legacy Wire (VLW) Messages....................................................... 170
Power Management ......................................................................................... 170
5.13.1 Features ............................................................................................. 170
5.13.2 PCH and System Power States ............................................................... 171
5.13.3 System Power Planes ............................................................................ 173
5.13.4 SMI#/SCI Generation ........................................................................... 173
5.13.4.1 PCI Express* SCI.................................................................... 175
5.13.4.2 PCI Express* Hot-Plug............................................................. 175
5.13.5 C-States ............................................................................................. 176
5.13.6 Dynamic PCI Clock Control (Mobile Only)................................................. 176
5.13.6.1 Conditions for Checking the PCI Clock........................................ 176
5.13.6.2 Conditions for Maintaining the PCI Clock .................................... 176
5.13.6.3 Conditions for Stopping the PCI Clock ........................................ 176
5.13.6.4 Conditions for Re-Starting the PCI Clock .................................... 177
Datasheet
5
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