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82V2084PFG: 产品描述TQFP-128, Tray; 产品类别无线/射频/通信电信电路; 文件大小1MB，共76页; 制造商IDT (Integrated Device Technology); 标准

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82V2084PFG在线购买

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82V2084PFG概述

TQFP-128, Tray

82V2084PFG规格参数

参数名称	属性值
Brand Name	Integrated Device Technology
是否无铅	不含铅
是否Rohs认证	符合
零件包装代码	TQFP
包装说明	LFQFP, QFP128,.63X.87,20
针数	128
制造商包装代码	PKG128
Reach Compliance Code	compli
ECCN代码	EAR99
JESD-30 代码	R-PQFP-G128
JESD-609代码	e3
长度	20 mm
湿度敏感等级	3
功能数量	1
端子数量	128
最高工作温度	85 °C
最低工作温度	-40 °C
封装主体材料	PLASTIC/EPOXY
封装代码	LFQFP
封装等效代码	QFP128,.63X.87,20
封装形状	RECTANGULAR
封装形式	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）	260
电源	3.3 V
认证状态	Not Qualified
座面最大高度	1.6 mm
最大压摆率	0.38 mA
标称供电电压	3.3 V
表面贴装	YES
电信集成电路类型	PCM TRANSCEIVER
温度等级	INDUSTRIAL
端子面层	Matte Tin (Sn) - annealed
端子形式	GULL WING
端子节距	0.5 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	30
宽度	14 mm
Base Number Matches	1

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QUAD CHANNEL T1/E1/J1 LONG HAUL/

SHORT HAUL LINE INTERFACE UNIT

IDT82V2084

FEATURES:

•

Four channel T1/E1/J1 long haul/short haul line interfaces

Supports HPS (Hitless Protection Switching) for 1+1 protection

without external relays

Receiver sensitivity exceeds -36 dB@772KHz and -43 dB@1024

KHz

Programmable T1/E1/J1 switchability allowing one bill of ma-

terial for any line condition

Single 3.3 V power supply with 5 V tolerance on digital interfaces

Meets or exceeds specifications in

ANSI T1.102, T1.403 and T1.408

- ITU I.431, G.703,G.736, G.775 and G.823

- ETSI 300-166, 300-233 and TBR 12/13

- AT&T Pub 62411

Per channel software selectable on:

- Wave-shaping templates for short haul and long haul LBO (Line Build

Out)

- Line terminating impedance (T1:100

Ω,

J1:110

Ω,

E1:75

Ω/120 Ω)

- Adjustment of arbitrary pulse shape

- JA (Jitter Attenuator) position (receive path or transmit path)

- Single rail/dual rail system interfaces

B8ZS/HDB3/AMI line encoding/decoding

- Active edge of transmit clock (TCLK) and receive clock (RCLK)

Active level of transmit data (TDATA) and receive data (RDATA)

Receiver or transmitter power down

High impedance setting for line drivers

PRBS (Pseudo Random Bit Sequence) generation and detection

with 2

-1 PRBS polynomials for E1

- QRSS (Quasi Random Sequence Signals) generation and detection

with 2

-1 QRSS polynomials for T1/J1

- 16-bit BPV (Bipolar Pulse Violation)/Excess Zero/PRBS or QRSS

error counter

- Analog loopback, Digital loopback, Remote loopback and Inband

loopback

Per channel cable attenuation indication

Adaptive receive sensitivity

Non-intrusive monitoring per ITU G.772 specification

Short circuit protection for line drivers

LOS (Loss Of Signal) & AIS (Alarm Indication Signal) detection

JTAG interface

Supports serial control interface, Motorola and Intel Non-Multi-

plexed interfaces

Package:

IDT82V2084: 128-pin TQFP

•

DESCRIPTION:

The IDT82V2084 can be configured as a quad T1, quad E1 or quad J1

Line Interface Unit. In receive path, an Adaptive Equalizer is integrated to

remove the distortion introduced by the cable attenuation. The IDT82V2084

also performs clock/data recovery, AMI/B8ZS/HDB3 line decoding and

detects and reports the LOS conditions. In transmit path, there is an AMI/

B8ZS/HDB3 encoder, Waveform Shaper and LBOs. There is one Jitter

Attenuator for each channel, which can be placed in either the receive path

or the transmit path. The Jitter Attenuator can also be disabled. The

IDT82V2084 supports both Single Rail and Dual Rail system interfaces and

both serial and parallel control interfaces. To facilitate the network mainte-

nance, a PRBS/QRSS generation/detection circuit is integrated in each

channel, and different types of loopbacks can be set on a per channel basis.

Four different kinds of line terminating impedance, 75Ω, 100

Ω,

110

Ω

and

120

Ω

are selectable on a per channel basis. The chip also provides driver

short-circuit protection and supports JTAG boundary scanning.

The IDT82V2084 can be used in SDH/SONET, LAN, WAN, Routers,

Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay

Access Devices, CSU/DSU equipment, etc.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGES

February 11,

2009

DSC-6221/5



QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

TABLE OF CONTENTS

IDT82V2084 PIN CONFIGURATIONS .......................................................................................... 8

PIN DESCRIPTION ....................................................................................................................... 9

FUNCTIONAL DESCRIPTION .................................................................................................... 14

3.1

T1/E1/J1 MODE SELECTION .......................................................................................... 14

3.2

TRANSMIT PATH ............................................................................................................. 14

3.2.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 14

3.2.2 ENCODER .............................................................................................................. 14

3.2.3 PULSE SHAPER .................................................................................................... 14

3.2.3.1 Preset Pulse Templates .......................................................................... 14

3.2.3.2 LBO (Line Build Out) ............................................................................... 15

3.2.3.3 User-Programmable Arbitrary Waveform ................................................ 15

3.2.4 TRANSMIT PATH LINE INTERFACE..................................................................... 19

3.2.5 TRANSMIT PATH POWER DOWN ........................................................................ 19

3.3

RECEIVE PATH ............................................................................................................... 20

3.3.1 RECEIVE INTERNAL TERMINATION.................................................................... 20

3.3.2 LINE MONITOR ...................................................................................................... 21

3.3.3 ADAPTIVE EQUALIZER......................................................................................... 21

3.3.4 RECEIVE SENSITIVITY ......................................................................................... 21

3.3.5 DATA SLICER ........................................................................................................ 21

3.3.6 CDR (Clock & Data Recovery)................................................................................ 21

3.3.7 DECODER .............................................................................................................. 21

3.3.8 RECEIVE PATH SYSTEM INTERFACE ................................................................ 21

3.3.9 RECEIVE PATH POWER DOWN........................................................................... 21

3.3.10 G.772 NON-INTRUSIVE MONITORING ................................................................ 22

3.4

JITTER ATTENUATOR .................................................................................................... 23

3.4.1 JITTER ATTENUATION FUNCTION DESCRIPTION ............................................ 23

3.4.2 JITTER ATTENUATOR PERFORMANCE ............................................................. 23

3.5

LOS AND AIS DETECTION ............................................................................................. 24

3.5.1 LOS DETECTION ................................................................................................... 24

3.5.2 AIS DETECTION .................................................................................................... 25

3.6

TRANSMIT AND DETECT INTERNAL PATTERNS ........................................................ 26

3.6.1 TRANSMIT ALL ONES ........................................................................................... 26

3.6.2 TRANSMIT ALL ZEROS......................................................................................... 26

3.6.3 PRBS/QRSS GENERATION AND DETECTION.................................................... 26

3.7

LOOPBACK ...................................................................................................................... 26

3.7.1 ANALOG LOOPBACK ............................................................................................ 26

3.7.2 DIGITAL LOOPBACK ............................................................................................. 26

3.7.3 REMOTE LOOPBACK............................................................................................ 26

3.7.4 INBAND LOOPBACK.............................................................................................. 28

3.7.4.1 Transmit Activate/Deactivate Loopback Code......................................... 28

3.7.4.2 Receive Activate/Deactivate Loopback Code.......................................... 28

3.7.4.3 Automatic Remote Loopback .................................................................. 28

QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

3.8

3.9

3.10

3.11

3.12

3.13

3.14

3.15

ERROR DETECTION/COUNTING AND INSERTION ...................................................... 29

3.8.1 DEFINITION OF LINE CODING ERROR ............................................................... 29

3.8.2 ERROR DETECTION AND COUNTING ................................................................ 29

3.8.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 30

LINE DRIVER FAILURE MONITORING ........................................................................... 30

MCLK AND TCLK ............................................................................................................. 31

3.10.1 MASTER CLOCK (MCLK) ...................................................................................... 31

3.10.2 TRANSMIT CLOCK (TCLK).................................................................................... 31

MICROCONTROLLER INTERFACES ............................................................................. 32

3.11.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 32

3.11.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 32

INTERRUPT HANDLING .................................................................................................. 33

5V TOLERANT I/O PINS .................................................................................................. 33

RESET OPERATION ........................................................................................................ 33

POWER SUPPLY ............................................................................................................. 33

PROGRAMMING INFORMATION .............................................................................................. 34

4.1

4.2

4.2.1 GLOBAL REGISTERS............................................................................................ 36

4.2.2 JITTER ATTENUATION CONTROL REGISTER ................................................... 37

4.2.3 TRANSMIT PATH CONTROL REGISTERS........................................................... 38

4.2.4 RECEIVE PATH CONTROL REGISTERS ............................................................. 40

4.2.5 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 42

4.2.6 INTERRUPT CONTROL REGISTERS ................................................................... 45

4.2.7 LINE STATUS REGISTERS ................................................................................... 48

4.2.8 INTERRUPT STATUS REGISTERS ...................................................................... 51

4.2.9 COUNTER REGISTERS ........................................................................................ 52

4.2.10 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 53

IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 54

5.1

JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 55

5.2

JTAG DATA REGISTER ................................................................................................... 55

5.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 55

5.2.2 BYPASS REGISTER (BR)...................................................................................... 55

5.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 55

5.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 56

TEST SPECIFICATIONS ............................................................................................................ 58

MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 70

7.1

SERIAL INTERFACE TIMING .......................................................................................... 70

7.2

PARALLEL INTERFACE TIMING ..................................................................................... 71

QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

LIST OF TABLES

Table-1

Table-2

Table-3

Table-4

Table-5

Table-6

Table-7

Table-8

Table-9

Table-10

Table-11

Table-12

Table-13

Table-14

Table-15

Table-16

Table-17

Table-18

Table-19

Table-20

Table-21

Table-22

Table-23

Table-24

Table-25

Table-26

Table-27

Table-28

Table-29

Table-30

Table-31

Table-32

Table-33

Table-34

Table-35

Table-36

Table-37

Table-38

Table-39

Table-40

Pin Description ................................................................................................................ 9

Transmit Waveform Value For E1 75

Ω

........................................................................ 16

Transmit Waveform Value For E1 120

Ω

...................................................................... 16

Transmit Waveform Value For T1 0~133 ft................................................................... 16

Transmit Waveform Value For T1 133~266 ft............................................................... 16

Transmit Waveform Value For T1 266~399 ft............................................................... 17

Transmit Waveform Value For T1 399~533 ft............................................................... 17

Transmit Waveform Value For T1 533~655 ft............................................................... 17

Transmit Waveform Value For J1 0~655 ft ................................................................... 17

Transmit Waveform Value For DS1 0 dB LBO.............................................................. 18

Transmit Waveform Value For DS1 -7.5 dB LBO ......................................................... 18

Transmit Waveform Value For DS1 -15.0 dB LBO ....................................................... 18

Transmit Waveform Value For DS1 -22.5 dB LBO ....................................................... 18

Impedance Matching for Transmitter ............................................................................ 19

Impedance Matching for Receiver ................................................................................ 20

Criteria of Starting Speed Adjustment........................................................................... 23

LOS Declare and Clear Criteria for Short Haul Mode ................................................... 24

LOS Declare and Clear Criteria for Long Haul Mode.................................................... 25

AIS Condition ................................................................................................................ 25

Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 26

EXZ Definition ............................................................................................................... 29

Interrupt Event............................................................................................................... 33

Global Register List and Map........................................................................................ 34

Per Channel Register List and Map .............................................................................. 35

ID: Chip Revision Register ............................................................................................ 36

RST: Reset Register ..................................................................................................... 36

GCF0: Global Configuration Register 0 ........................................................................ 36

GCF1: Global Configuration Register 1 ........................................................................ 37

INTCH: Interrupt Channel Indication Register............................................................... 37

JACF: Jitter Attenuator Configuration Register ............................................................. 37

TCF0: Transmitter Configuration Register 0 ................................................................. 38

TCF1: Transmitter Configuration Register 1 ................................................................. 38

TCF2: Transmitter Configuration Register 2 ................................................................. 39

TCF3: Transmitter Configuration Register 3 ................................................................. 39

TCF4: Transmitter Configuration Register 4 ................................................................. 39

RCF0: Receiver Configuration Register 0..................................................................... 40

RCF1: Receiver Configuration Register 1..................................................................... 41

RCF2: Receiver Configuration Register 2..................................................................... 42

MAINT0: Maintenance Function Control Register 0...................................................... 42

MAINT1: Maintenance Function Control Register 1...................................................... 43

82V2084PFG

82V2084PFG在线购买

82V2084PFG概述

82V2084PFG规格参数

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