Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode
logic level field-effect power
transistor in a plastic full-pack
envelope.
The device is intended for use in
Switched Mode Power Supplies
(SMPS), motor control, welding,
DC/DC and AC/DC converters, and
in automotive and general purpose
switching applications.
BUK542-60A/B
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
R
DS(ON)
PARAMETER
BUK542
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state
resistance;
V
GS
= 5 V
MAX.
-60A
60
9.2
22
0.15
MAX.
-60B
60
8.4
22
0.18
UNIT
V
A
W
Ω
PINNING - SOT186
PIN
1
2
3
gate
drain
source
DESCRIPTION
PIN CONFIGURATION
case
SYMBOL
d
g
case isolated
1 2 3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±V
GS
±V
GSM
I
D
I
D
I
DM
P
tot
T
stg
T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Non-repetitive gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage temperature
Junction Temperature
CONDITIONS
-
R
GS
= 20 kΩ
-
t
p
≤
50
µs
T
hs
= 25 ˚C
T
hs
= 100 ˚C
T
hs
= 25 ˚C
T
hs
= 25 ˚C
-
-
MIN.
-
-
-
-
-
-
-
-
- 55
-
-60A
9.2
5.8
37
22
150
150
MAX.
60
60
15
20
-60B
8.4
5.3
33
UNIT
V
V
V
V
A
A
A
W
˚C
˚C
THERMAL RESISTANCES
SYMBOL
R
th j-hs
R
th j-a
PARAMETER
Thermal resistance junction to
heatsink
Thermal resistance junction to
ambient
CONDITIONS
with heatsink compound
MIN.
-
-
TYP.
-
55
MAX.
5.68
-
UNIT
K/W
K/W
August 1994
1
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
STATIC CHARACTERISTICS
T
hs
= 25 ˚C unless otherwise specified
SYMBOL
V
(BR)DSS
V
GS(TO)
I
DSS
I
DSS
I
GSS
R
DS(ON)
PARAMETER
Drain-source breakdown
voltage
Gate threshold voltage
Zero gate voltage drain current
Zero gate voltage drain current
Gate source leakage current
Drain-source on-state
resistance
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA
V
DS
= V
GS
; I
D
= 1 mA
V
DS
= 60 V; V
GS
= 0 V; T
j
= 25 ˚C
V
DS
= 60 V; V
GS
= 0 V; T
j
=125 ˚C
V
GS
=
±15
V; V
DS
= 0 V
V
GS
= 5 V;
BUK542-60A
BUK542-60B
I
D
= 8.5 A
MIN.
60
1.0
-
-
-
-
-
BUK542-60A/B
TYP.
-
1.5
1
0.1
10
0.12
0.15
MAX.
-
2.0
10
1.0
100
0.15
0.18
UNIT
V
V
µA
mA
nA
Ω
Ω
DYNAMIC CHARACTERISTICS
T
hs
= 25 ˚C unless otherwise specified
SYMBOL
g
fs
C
iss
C
oss
C
rss
t
d on
t
r
t
d off
t
f
L
d
L
s
PARAMETER
Forward transconductance
Input capacitance
Output capacitance
Feedback capacitance
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal source inductance
CONDITIONS
V
DS
= 25 V; I
D
= 8.5 A
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
V
DD
= 30 V; I
D
= 3 A;
V
GS
= 5 V; R
GS
= 50
Ω;
R
gen
= 50
Ω
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
MIN.
5
-
-
-
-
-
-
-
-
-
TYP.
6.7
400
150
65
12
60
50
45
4.5
7.5
MAX.
-
600
200
100
18
80
70
70
-
-
UNIT
S
pF
pF
pF
ns
ns
ns
ns
nH
nH
ISOLATION LIMITING VALUE & CHARACTERISTIC
T
hs
= 25 ˚C unless otherwise specified
SYMBOL
V
isol
PARAMETER
Repetitive peak voltage from all
three terminals to external
heatsink
CONDITIONS
R.H.
≤
65% ; clean and dustfree
MIN.
-
TYP.
MAX.
1500
UNIT
V
C
isol
Capacitance from T2 to external f = 1 MHz
heatsink
-
12
-
pF
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
hs
= 25 ˚C unless otherwise specified
SYMBOL
I
DR
I
DRM
V
SD
t
rr
Q
rr
PARAMETER
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
-
-
I
F
= 9.2 A ; V
GS
= 0 V
I
F
= 9.2 A; -dI
F
/dt = 100 A/µs;
V
GS
= 0 V; V
R
= 30 V
MIN.
-
-
-
-
-
TYP.
-
-
1.3
60
0.15
MAX.
9.2
37
1.7
-
-
UNIT
A
A
V
ns
µC
August 1994
2
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
AVALANCHE LIMITING VALUE
T
hs
= 25 ˚C unless otherwise specified
SYMBOL
W
DSS
PARAMETER
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
I
D
= 14 A ; V
DD
≤
25 V ;
V
GS
= 5 V ; R
GS
= 50
Ω
MIN.
-
BUK542-60A/B
TYP.
-
MAX.
30
UNIT
mJ
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
with heatsink compound
100
ID / A
S/
VD
ID
BUK542-60
A
B
10
O
S(
RD
=
N)
tp = 10 us
100 us
1 ms
1
DC
10 ms
100 ms
0
20
40
60
80
Ths / C
100
120
140
0.1
1
10
VDS / V
100
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
hs
)
Normalised Current Derating
with heatsink compound
Fig.3. Safe operating area. T
hs
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
120
110
100
90
80
70
60
50
40
30
20
10
0
ID%
1E+01
Zth j-hs / (K/W)
0.5
ZTHX42
1E+00
0.2
0.1
0.05
0.02
P
D
t
p
D=
t
p
T
t
1E-01
0
0
20
40
60
80
Ths / C
100
120
140
1E-02
1E-07
T
1E-05
1E-03
t/s
1E-01
1E+01
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
hs
); conditions: V
GS
≥
5 V
Fig.4. Transient thermal impedance.
Z
th j-hs
= f(t); parameter D = t
p
/T
August 1994
3
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
BUK542-60A/B
28
24
20
16
12
8
4
0
ID / A
10
7
BUK552-60A
6
7
6
gfs / S
BUK 552-60A
5
5
4
VGS / V =
4
3
2
3
1
0
0
2
4
VDS / V
6
8
10
0
4
8
12
16
ID / A
20
24
28
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
RDS(ON) / Ohm
3
3.5
4
4.5
5
BUK552-60A
VGS / V =
5.5
6
7
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
a
0.5
Normalised RDS(ON) = f(Tj)
0.4
1.5
0.3
1.0
0.2
10
0.5
0.1
0
0
10
20
ID / A
30
40
0
-60 -40 -20
0
20
40 60
Tj / C
80
100 120 140
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
ID / A
BUK552-60A
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 8.5 A; V
GS
= 5 V
VGS(TO) / V
max.
28
24
20
16
12
8
4
0
Tj / C =
25
150
2
typ.
min.
1
0
0
2
4
VGS / V
6
8
-60
-40
-20
0
20
40
60
Tj / C
80
100
120
140
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
August 1994
4
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
BUK542-60A/B
1E-01
ID / A
SUB-THRESHOLD CONDUCTION
30
IF / A
BUK552-60A
1E-02
2%
98 %
1E-03
typ
20
1E-04
10
1E-05
Tj / C = 150
25
1E-06
0
0.4
0.8
1.2
VGS / V
1.6
2
2.4
0
0
1
VSDS / V
2
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
C / pF
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
WDSS%
10000
BUK5y2-50
120
110
100
90
1000
Ciss
Coss
Crss
80
70
60
50
40
30
20
10
100
10
0
20
VDS / V
40
0
20
40
60
80
100
Ths / C
120
140
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
VGS / V
BUK552-60
VDS / V = 12
10
8
6
4
2
0
0
2
4
6
8
10
QG / nC
12
14
16
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
hs
); conditions: I
D
= 14 A
12
+
L
VDS
VGS
0
RGS
T.U.T.
R 01
shunt
VDD
48
-
-ID/100
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 14 A; parameter V
DS
Fig.16. Avalanche energy test circuit.
2
W
DSS
=
0.5
⋅
LI
D
⋅
BV
DSS
/(BV
DSS
−
V
DD
)
August 1994
5
Rev 1.100
嵌入式系统
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