HY5DU281622FT(P)-xI Series
DESCRIPTION
The HY5DU281622FT(P)-xI is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for
the main memory applications which requires large memory density and high bandwidth.
This Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
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V
DD
, V
DDQ
= 2.3V min ~ 2.7V max
(Typical 2.5V Operation +/- 0.2V for DDR266, 333)
V
DD
, V
DDQ
= 2.4V min ~ 2.7V max
(Typical 2.6V Operation +0.1/- 0.2V for DDR400,
400Mbps/pin product and 500Mbps/pin product )
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
On chip DLL align DQ and DQS transition with CK
transition
DM mask write data-in at the both rising and falling
edges of the data strobe
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All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
Programmable CAS latency 2/2.5 (DDR266, 333)
and 3/4 (DDR400, 400Mbps/pin product and
500Mbps/pin product) supported
Programmable burst length 2/4/8 with both sequen-
tial and interleave mode
Internal four bank operations with single pulsed
/RAS
Auto refresh and self refresh supported
t
RAS
lock out function supported
4096 refresh cycles/64ms
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
Lead free (*ROHS Compliant)
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ORDERING INFORMATION
Part No.
HY5DU281622F(L)TP-xI*
OPERATING FREQUENCY
Grade
-4
-5
-D43
-D4
-J
-K
-H
Configuration Package
400mil
8Mx16
66pin
TSOP-II**
Clock Rate
250MHz@CL4
200MHz@CL3 / 100MHz @CL2
200MHz@CL3 / 100MHz @CL2
200MHz@CL3 / 100MHz @CL2
133MHz@CL2
133MHz@CL2
100MHz@CL2
166MHz @CL2.5
& @CL3
133MHz@CL2.5
133MHz@CL2.5
Remark
500Mbps/pin
(maximum Date rate)
400Mbps/pin
(maximum Date rate)
DDR400B (3-3-3)
DDR400 (3-4-4)
DDR333 (2.5-3-3)
DDR333 (3-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
* X means speed grade
** Lead-free product
*ROHS (Restriction Of Hazardous Substances)
Rev. 1.0 / June 2008
3
HY5DU281622FT(P)-xI Series
PIN DESCRIPTION
PIN
CK, /CK
TYPE
Input
DESCRIPTION
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for
SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output dis-
able. CKE must be maintained high throughout READ and WRITE accesses. Input buff-
ers, excluding CK, /CK and CKE are disabled during POWER DOWN. Input buffers,
excluding CKE are disabled during SELF REFRESH. CKE is an SSTL_2 input, but will
detect an LVCMOS LOW level after V
DD
is applied.
Chip Select: Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-
mands are masked when Chip Select is registered high. Chip Select provides for exter-
nal bank selection on systems with multiple banks. Chip Select is considered part of the
command code.
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or
PRECHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands, and the column
address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 is sampled during a precharge
command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all
banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0,
BA1. The address inputs also provide the op code during a MODE REGISTER SET com-
mand. BA0 and BA1 define which mode register is loaded during the MODE REGISTER
SET command (MRS or EMRS).
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with that input data during a WRITE access. DM is sampled
on both edges of DQS. Although DM pins are input only, the DM loading matches the
DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM cor-
responds to the data on DQ8-Q15.
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. For the x16, LDQS corresponds to
the data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15.
Data input / output pin: Data bus
Power supply for internal circuits and input buffers.
Power supply for output buffers for noise immunity.
Reference voltage for inputs for SSTL interface.
No connection.
CKE
Input
/CS
Input
BA0, BA1
Input
A0 ~ A11
Input
/RAS, /CAS, /
WE
Input
DM
(LDM,UDM)
Input
DQS
(LDQS,UDQS)
DQ
V
DD
/ V
SS
V
DDQ
/ V
SSQ
V
REF
NC
I/O
I/O
Supply
Supply
Supply
NC
Rev. 1.0 / June 2008
5
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