Ordering number : ENA0432A
LC87F06J2A
CMOS IC
FROM 192K byte, RAM 8192 byte on-chip
8-bit 1-chip Microcontroller
Overview
http://onsemi.com
The LC87F06J2A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
66.6ns, integrate on a single chip a number of hardware features such as 192K-byte flash ROM (onboard rewritable),
8K-byte RAM, Onchip debugging function, two sophisticated 16-bit timers/counters (may be divided into 8-bit
timers), a 16-bit timer with a prescaler (may be divided into 8-bit timers), four 8-bit timers with a prescaler, a base
timer serving as a time-of-day clock, two synchronous SIO ports (with automatic block transmission/reception
capabilities), an asynchronous/synchronous SIO port, two synchronous SIO ports, two UART ports (full duplex), four
12-bit PWM channels, VPS/PDC/PAL-WSS
•
XDS
•
EPG-J
•
VBID(Video-ID) Data-slicer, an universal remote
control transmitter, an 8-bit 16-channel AD converter, a high-speed clock counter, a system clock frequency divider,
and a 36-source 10-vector interrupt, ROM correction function feature.
Features
Flash
ROM
•
Single 5V power supply, on-board writeable
•
Block erase in 128 byte units
•
196608 × 8 bits (LC87F06J2A)
RAM
•
8192 × 9 bits
Bus
Cycle Time
•
66.6ns (15MHz, 1/1 frequency division ratio )
Note: Bus cycle time indicates the speed to read ROM.
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.003
31407HKIM 20070115-S00002 No.A0432-1/32
LC87F06J2A
Minimum
Instruction Cycle Time (tCYC)
•
200ns (15MHz, 1/1 frequency division ratio)
Ports
•
Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1 bit units: 75 (P1n, P2n, P3n, P70 to P73, P8n, PAn, PB0 to PB2,
PCn, S2Pn, XT2, PWM0, PWM1, PEn, PFn )
Ports whose I/O direction can be designated in 4 bit units: 8 (P0n)
•
Normal withstand voltage input ports:
1 (XT1)
•
Dedicated oscillator ports:
2 (CF1, CF2)
•
Reset pin:
1 (RES)
•
Data slicer pins:
2 (PB4, PB6)
•
Power pins:
11 (VSS1 to VSS4, VDD1 to VDD4,
VSSVCO, VDDVCO, VDDODA)
Timer
•
Timer 0: 16-bit timer/counter with capture register
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers)
+ 8-bit counter (with two 8-bit capture registers)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3: 16-bit counter (with two 16-bit capture registers)
•
Timer 1: 16-bit timer/counter that support PWM/ toggle output
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs)
+ 8-bit timer/counter (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM.)
•
Timer 4: 8-bit timer with a 6-bit prescaler
•
Timer 5: 8-bit timer with a 6-bit prescaler
•
Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
•
Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
•
Timer 8: 16-bit timer with a prescaler (may be divided into 8-bit timers)
•
Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillator), system clock,
and timer 0 prescaler output.
2) Interrupts programmable in 5 different time schemes.
Day
and Time Counter
1) Using with a base timer, it can be used as 65,000 days + minute + second counter.
High-speed
Clock Counter
1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
2) Can generate output real time.
SIO
•
SIO 0: 8 bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits)
•
SIO 1: 8 bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (Half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
Continued on next page.
No.A0432-2/32
LC87F06J2A
Continued from preceding page.
•
SIO2: 8 bit synchronous serial interface
1) LSB first mode
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 32 bytes)
•
SIO 7: 8 bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
•
SIO 8: 8 bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
UART:
2 channels
1) Full duplex
2) 7/8/9 bit data bits selectable
3) 1 stop bit (2 bits in continuous transmission mode)
4) Built-in baudrate generator (with baudrates of 16/3 to 8192/3 tCYC)
AD
Converter
•
8 bits × 16 channels
PWM
•
Multifrequency 12-bit PWM × 4 channels
Remote
Control Receiver Circuit (sharing pins with P73, INT3, T0IN and TOHCP)
1) Noise filtering function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read
with an instruction, the signal level at that pin is read regardless of the availability of the noise filtering function.
Small
Signal Detect Function
1) Small Signal Detect Function is available in the following two terminals.
P20/INT4/T1IN/T0LCP/T0HCP/INT6/T0LCP1/SSGI0
P24/INT5/T1IN/T0LCP/T0HCP/INT7/T0HCP1/SSGI1
2) Capable of detecting a pulse with certain level of amplitude.
3) Input bias circuit available.
H-Counter
1) H-counter can choose one of the following signals as count-clock.
HCTR signal of P22/INT4/T1IN/T0LCP/T0HCP/HCTR terminal
CSYNC signal of PB6/CVD/CSYNC terminal
Composite sync signal detected from CVD (composite Video) signal by built-in sync-separator inputted form
PB6/CVD/CSYNC terminal
2) Counter 7bit (up) + 1bit (over-flow flag)
Field
(first/second) Detect Function
1) Distinguishes a field with one of the following signals.
CSYNC signal of PB6/CVD/CSYNC terminal
Composite sync signal detected from CVD (composite Video) signal by built-in sync-separator inputted form
PB6/CVD/CSYNC terminal
2) Outputs Field-Detect signal from PB0/DS1FLD terminal
Watchdog
Timer
1) External RC watchdog timer
2) Interrupt and reset signals selectable
No.A0432-3/32
LC87F06J2A
Data-Slicer
•
XDS
1) Supports XDS-1X and XDS-2X (With auto-recognition)
•
VPS/PDC/PAL-WSS
Data-slicer can choose one of the following three formats to the TV Line(VBI).
1) PDC/UDT and other Teletext data
2) VPS
3) PAL-WSS
•
VPS
•
EPG-J
•
Antiope
•
VBID(VideoID)
Universal
Remote Control Transmitter Circuit
•
Outputs remote control signal from PF4/IRP terminal.
Interrupts
•
36 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control.
Any interrupt requests of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
1
2
3
4
5
6
7
8
9
10
Vector
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Selectable Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
INT0
INT1
INT2/T0L/INT4
INT3/INT5/Base timer0/Base timer1/Remocon transmit
T0H/INT6/SIO7
T1L/T1H/INT7/SIO8
SIO0/UART1 receive/UART2 receive/T8L/T8H
SIO1/SIO2/UART1 transmit/UART2 transmit
ADC/T6/T7/PWM4, PWM5/ Automatic transmission
Port 0/T4/T5/Data slicer /PWM0, PWM1
Interrupt signal
•
Priority Level: X > H > L
•
Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine
Stack Levels
•
4096 levels maximum (the stack is allocated in RAM.)
High-speed
Multiplication/Division Instructions
•
16 bits
×
8 bits
(5 tCYC execution time)
•
24 bits
×
16 bits
(12 tCYC execution time)
•
16 bits
÷
8 bits
(8 tCYC execution time)
•
24 bits
÷
16 bits
(12 tCYC execution time)
Oscillation
Circuits
•
RC oscillator circuit (internal): For system clock
•
CF oscillator circuit: For system clock with internal Rf
•
Crystal oscillator circuit: For low-speed system clock
•
Multifrequency RC oscillator circuit (internal): For system clock
No.A0432-4/32
LC87F06J2A
System
Clock Divider Function
•
Can run on low current.
•
The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8μs
(at a main clock rate of 10MHz).
Standby
Function
•
HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by system reset or occurrence of interrupt.
•
HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the Reset pin to the lower level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
•
X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer
and the Day-and-time counter.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the Reset pin to the low level.
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level.
(3) Having an interrupt source established at port 0.
(4) Having an interrupt source established in the base timer circuit.
Onchip
Debugging
•
Permits software debugging with the test device installed on the target board.
ROM
Correction Function
•
PC match address registers: 4
•
Ram for ROM correction: 128byte
Package
Form
•
QIP100E(14×20): “Lead-free type”
Development
Tools
•
On-chip debugger: TCB87 TypeA + LC87F06J2A
: TCB87 TypeB + LC87F06J2A
Flash
ROM Programming Boards
Package
QIP100E(14×20)
Programming boards
W87F05256Q
Flash
ROM Programmer
Maker
Flash Support Group, Inc.
(Single)
Flash Support Group, Inc.
(Gang)
Model
AF9708/AF9709/AF9709B
(including product of Ando Electric Co.,Ltd)
AF9723(Main body)
(including product of Ando Electric Co.,Ltd)
AF9833(Unit)
(including product of Ando Electric Co.,Ltd)
Our company
SKK(Sanyo FWS)
Application Version: After 1.03
Chip Data Version: After 2.01
LC87F06J2
Revision: After 01.86
Revision: After 02.04
LC87F06J2A FAST
Supported version
Revision: After 02.61
Device
LC87F06J2A FAST
No.A0432-5/32
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