CMOS LSI
No. 5487
LC66P2316
Four-Bit Single-Chip Microcontroller
with 16 KB of On-Chip OTP PROM
Preliminary
Overview
The LC66P2316 is an on-chip OTP PROM version of the
LC6623XX Series CMOS 4-bit single-chip micro-
controllers. The LC66P2316 is appropriate for program
development and product evaluation since it provides
identical functionality and pin compatibility with the
LC662316A.
Package Dimensions
unit: mm
3025B-DIP42S
[LC66P2316]
42
22
15.24
• On-chip OTP ROM capacity of 16 kilobytes, and an on-
chip RAM capacity of 512
×
4 bits.
• Fully supports the LC66000 Series common instruction
set (128 instructions).
• I/O ports: 36 pins
• DTMF generator
This microcontroller incorporates a circuit that can
generate two sine wave outputs, DTMF output, or a
melody output for software applications.
• 8-bit serial interface: one circuit
• Instruction cycle time: 0.95 to 10 µs (at 4.0 to 5.5 V)
• Powerful timer functions and prescalers
— Time limit timer, event counter, pulse width
measurement, and square wave output using a 12-bit
timer.
— Time limit timer, event counter, PWM output, and
square wave output using an 8-bit timer.
— Time base function using a 12-bit prescaler.
• Powerful interrupt system with 10 interrupt factors and 7
interrupt vector locations.
— External interrupts: 3 factors/3 vector locations
— Internal interrupts: 4 factors/4 vector locations
(Waveform output internal interrupts: 3 factors and 1
vector; shared with external expansion interrupts)
• Flexible I/O functions
Selectable options include 20-mA drive outputs, inverter
circuits, pull-up and open drain circuits.
• Optional runaway detection function (watchdog timer)
• 8-bit I/O functions
• Power saving functions using halt and hold modes.
• Packages: DIP42S, QIP48E (QFP48E)
• Evaluation LSIs: LC66599 (evaluation chip) +
EVA800/850-TB662YXX2
13.8
Features and Functions
1
37.9
4.25
21
0.95
0.48
1.78
0.51
min
1.15
SANYO: DIP42S
unit: mm
3156-QFP48E
[LC66P2316]
17.2
1.5
36
1.5
37
1.0
14.0
1.6
1.5
25
24
0.15
17.2
14.0
1.6
1.5
1.0
48
1
0.35
13
12
0.1
2.70
(STAND OFF)
3.0max
0.8
15.6
SANYO: QFP48E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
22897HA (OT) No. 5487-1/27
3.8
5.1
max
0.25
LC66P2316
Series Organization
Type No.
LC66304A/306A/308A
LC66404A/406A/408A
LC66506B/508B/512B/516B
LC66354A/356A/358A
LC66354S/356S/358S
LC66556A/558A/562A/566A
LC66354B/356B/358B
LC66556B/558B/562B/566B
LC66354C/356C/358C
LC662104A/06A/08A
LC662304A/06A/08A/12A/16A
LC662508A/12A/16A
LC665304A/06A/08A/12A/16A
LC66E308
LC66P308
LC66E408
LC66P408
LC66E516
LC66P516
LC66E2108*
LC66E2316
LC66E2516
LC66E5316
LC66P2108*
LC66P2316*
LC66P2516
LC66P5316
Note:
*
Under development
No. of
pins
42
42
64
42
42
64
42
64
42
30
42
64
48
42
42
42
42
64
64
30
42
64
52/48
30
42
64
48
ROM capacity
4 K/6 K/8 KB
4 K/6 K/8 KB
6 K/8 K/12 K/16 KB
4 K/6 K/8 KB
4 K/6 K/8 KB
6 K/8 K/12 K/16 KB
4 K/6 K/8 KB
6 K/8 K/12 K/16 KB
4 K/6 K/8 KB
4 K/6 K/8 KB
RAM
capacity
512 W
512 W
512 W
512 W
512 W
512 W
512 W
512 W
512 W
384 W
DIP64S
DIP42S
DIP64S
DIP42S
DIP30SD
DIP42S
DIP64S
DIP48S
DIC42S
with window
DIP42S
DIC42S
with window
DIP42S
DIC64S
with window
DIP64S
DIP42S
DIP42S
DIP64S
DIP42S
Package
QFP48E
QFP48E
QFP64A
QFP48E
QFP44M
QFP64E
QFP48E
QFP64E
QFP48E
MFP30S
QFP48E
QFP64E
QFP48E
QFC48
with window
QFP48E
QFC48
with window
QFP48E
QFC64
with window
QFP64E
Window and OTP evaluation versions
4.5 to 5.5 V/0.92 µs
Dual oscillator support
3.0 to 5.5 V/0.95 µs
On-chip DTMF generator versions
3.0 to 5.5 V/0.95 µs
Low-voltage versions
2.2 to 5.5 V/3.92 µs
Low-voltage high-speed versions
3.0 to 5.5 V/0.92 µs
2.5 to 5.5 V/0.92 µs
Normal versions
4.0 to 6.0 V/0.92 µs
Features
4 K/6 K/8 K/12 K/16 KB 512 W
8 K/12 K/16 KB
512 W
4 K/6 K/8 K/12 K/16 KB 512 W
EPROM 8 KB
OTPROM 8 KB
EPROM 8 KB
OTPROM 8 KB
EPROM 16 KB
OTPROM 16 KB
EPROM 8 KB
EPROM 16 KB
EPROM 16 KB
EPROM 16 KB
OTPROM 8 KB
OTPROM 16 KB
OTPROM 16 KB
OTPROM 16 KB
512 W
512 W
512 W
512 W
512 W
512 W
384 W
512 W
512 W
512 W
384 W
512 W
512 W
512 W
DIC42S
with window
DIC64S
with window
DIC52S
with window
DIP30SD
DIP42S
DIP64S
DIP48S
QFC48
with window
QFC64
with window
QFC48
with window
MFP30S
QFP48E
QFP64E
QFP48E
Window evaluation versions
4.5 to 5.5 V/0.92 µs
OTP
4.0 to 5.5 V/0.95 µs
No. 5487-2/27
LC66P2316
Pin Assignments
DIP42S
P20/SI0/A0
P21/SO0/A1
P22/SCK0/A2
P23/INT0/A3
P30/INT1/A4
P31/POUT0/A5
P32/POUT1/A6
VSS
OSC1
OSC2
VDD
RES/VPP/OE
PE0
PE1
TEST/EPMOD
P33/HOLD
P40/INV0I/A7
P41/INV0O/A8
P42/INV1I/A9
P43/INV1O/A10
P50/A11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P13/D7
P12/D6
P11/D5
P10/D4
P03/D3
P02/D2
P01/D1
P00/D0
PD3/INV3O
PD2/INV3I
PD1/INV2O
PD0/INV2I
PC3/DASEC
PC2/CE
P63/PIN1
P62/DT
P61
P60/ML
P53/INT2/TA
P52/A13
P51/A12
LC66P2316
QFP48E
P02/D2
P01/D1
P00/D0
PD3/INV30
PD2/INV31
PD1/INV20
NC
PD0/INV21
PC3/DASEC
PC2/CE
P63/PIN
P62/DT
P03/D3
P10/D4
P11/D5
P12/D6
P13/D7
NC
NC
P20/SI0/A0
P21/SO0/A1
P22/SCK0/A2
P23/INT0/A3
P30/INT1/A4
36 35 34 33 32 31 30 29 28 27 26 25
37
24
38
23
39
22
40
21
LC66P2316
41
20
42
19
43
18
44
17
45
16
46
15
47
14
48
13
1 2 3 4 5 6 7 8 9 10 11 12
P31/POUT0/A5
P32/POUT1/A6
VSS
OSC1
OSC2
NC
VDD
RES/VPP/OE
PE0
PE1
TEST/EPMOD
P33/HOLD
P61/DP
P60/ML
P53/TA
P52/A13
P51/A12
NC
NC
P50/A11
P43/INV10/A10
P42/INV11/A9
P41/INV00/A8
P40/INV01/A7
Top view
We recommend the use of reflow-soldering techniques to solder-mount QFP packages.
Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly
immersed in a dip-soldering bath (dip-soldering techniques).
No. 5487-3/27
LC66P2316
Usage Notes
The LC66P2316 was created for program development, product evaluation, and prototype development for products
based on the LC6623XX Series microcontrollers. Keep the following points in mind when using this product.
1. After a reset
The RES pin must be held low for an additional 3 instruction cycles after the oscillator stabilization period has
elapsed. Also, the port output circuit types are set up during the 9 instruction cycles immediately after RES is set
high. Only then is the program counter set to 0 and program execution started from that location. (The port output
circuits all revert to the open-drain type during periods when RES is low.)
VDD
min
VDD
OSC
At least 10 ms
Oscillator
stabilization
At least 3
instruction
RES
Program execution (PC)
Open drain
Location Location
0
1
Port output type
Option switching
Option specification
period
9 instruction
cycles
2. Notes on LC6623XX evaluation
The high end of the EPROM area (locations 3FF0H to 3FFFH) are the option specification area. Option specification
data must be programmed for and loaded into this area. The Sanyo specified cross assembler for this product is the
program LC66S.EXE. Also, insert JMP instructions so that user programs do not attempt to execute addresses that
exceed the capacity of the mask ROM, and write zeros (00H) to areas (other than 3FF0H to 3FFFH) that exceed the
actual capacity of the mask ROM.
3. Mounting notes
Due to structural considerations, Sanyo is unable to fully test one-time programmable products. Therefore, the user
must apply the screening procedure described on page 20 to these products.
4. Use the following procedure when ordering ROM through the Sanyo PROM writing service. (Note that this is a for-
fee service.)
• If ordering one-time programmable and mask ROM versions at the same time:
The customer must provide the EPROM for the mask ROM version, the order forms for the mask ROM version,
and the order forms for the one-time programmable version.
• If ordering only the one-time programmable version:
The customer must provide the EPROM and the order forms for the one-time programmable version. The last
section of the EPROM (locations 3FF0H to 3FFFH) is the option specification area, and the option specification
data must be written to this area. The Sanyo specified cross assembler for this product is the program LC66S.EXE.
Also, insert JMP instructions so that user programs do not attempt to execute addresses that exceed the capacity of
the mask ROM, and write zeros (00H) to areas (other than 3FF0H to 3FFFH) that exceed the actual capacity of the
mask ROM.
5. Differences between this product and the mask ROM version:
Carefully read the sections on the following pages that describe these differences.
No. 5487-4/27
LC66P2316
Main differences between the LC66E2316, LC66P2316, and LC6623XX Series
Item
Differences in the main
characteristics
• Operating temperature range
• Operating supply voltage/operating
frequency (cycle time)
• Input high-level current (RES)
• Input low-level current (RES)
• Current drain
(Operating at 4 MHz)
(Halt mode at 4 MHz)
(Hold mode)
Port output types at reset
Package
LC6623XX Series (mask version)
–30 to +70°C
LC66E2316
+10 to +40°C
LC66P2316
–30 to +70°C
3.5 to 5.5 V/0.95 to 10 µs
4.5 to 5.5 V/0.95 to 10 µs
Typical: 10 µA
(normal operation and halt mode)
Hold mode: 1 µA maximum
Typical: 100 µA
Larger than that for the mask versions
Typical: 10 nA, maximum: 10 µA*
4.0 to 5.5 V/0.95 to 10 µs
Typical: 10 µA
(normal operation and halt mode)
Hold mode: 1 µA maximum
Typical: 100 µA
Larger than that for the mask versions
Typical: 10 nA, maximum: 10 µA*
Maximum: 1 µA
Maximum: 1 µA
Typical: 10 nA, maximum: 10 µA
The output type specified in
the options
• DIP42S
• QFP48E
Open-drain outputs
• DIC42S window package
• QFC48 window package
Open-drain outputs
• DIP42S
• QFP48E
Note:
*
Although the microcontroller will remain in hold mode if the RES pin is set low while it is in hold mode, always use the reset start sequence (after
switching HOLD from low to high, switch RES from low to high) when clearing hold mode. Also not that a current of about 100 µA flows from the
RES pin when it is low. This increases the hold mode current drain by about 100 µA.
See the data sheets for the individual products for details on other differences.
System Block Diagram
RAM STACK
(512W)
SYSTEM
CONTROL
FLAG
E DD DD
SP M P P P P
R HL XY
C
Z
RES
TEST
OSC1
OSC2
HOLD
OTPROM
16KB
EPROM
control
A0 to A13
D0 to D7
CE
DASEC
Vpp/OE
EPMOD
TA
E
A
ALU
PC
ML
DT
DTMF
GEN.
PRESCALER
MPX
TIMER0
SERIAL I/O 0
POUT0
SI0
SO0
SCK0
INT0
INT1. INT2
PE
PD
PC
MPX
INTERRUPT
CONTROL
MPX
TIMER1
PIN1. POUT1
INV
x
O
INV
x
I
(x=0 to 3)
P0
P1
P2
P3
P4
P5
P6
No. 5487-5/27
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
